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* other brands and names are the property of their respective owners. information in this document is provided in connection with intel products. intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of intel products except as provided in intel's terms and conditions of sale for such products. intel retains the right to make changes to these specifications at any time, without notice. microcomputer products may have minor variations to this specification known as errata. march 1996 copyright ? intel corporation, 1996 order number: 290476-004 82374eb/82374SB eisa system component (esc) y integrates eisa compatible bus controller e translates cycles between eisa and isa bus e supports eisa burst and standard cycles e supports isa zero wait-state cycles e supports byte assembly/ disassembly for 8-, 16- and 32-bit transfers e supports eisa bus frequency of up to 8.33 mhz y supports eight eisa slots e directly drives address, data and control signals for eight slots e decodes address for eight slot specific aens y provides enhanced dma controller e provides scatter-gather function e supports type a, type b, type c (burst), and compatible dma transfer e provides seven independently programmable channels e integrates two 82c37a compatible dma controllers y integrates the functionality of two 82c59 interrupt controllers and two 82c54 timers e provides 14 programmable channels for edge or level interrupts e provides 4 pci interrupts routible to any of 11 interrupt channels e supports timer function for refresh request, system timer, speaker tone, fail safe timer, and cpu speed control y advanced programmable interrupt controller (apic) e multiprocessor interrupt management e separate bus for interrupt messages y 5v cmos technology y provides high performance arbitration e supports eight eisa masters and pceb e supports isa masters, dma channels, and refresh e provides programmable arbitration scheme for fixed, rotating, or combination priority y integrates support logic for x-bus peripherals e generates chip selects/encoded chip selects for floppy and keyboard controller, ide, parallel/ serial ports , and general purpose peripherals e provides interface for real time clock e generates control signals for x-bus data transceiver e integrates port 92, mouse interrupt, and coprocessor error reporting y generates non-maskable interrupts (nmi) e pci system errors e pci parity errors e eisa bus parity errors e fail safe timer e bus timeout e via software control y provides bios interface e supports 512k bytes of flash or eprom bios on the x-bus e allows bios on pci e supports integrated vga bios y 82374SB system power management (intel smm support) e fast on/off support via smi generationhardware events, software events, extsmi y , fast off timer, system events e programmable cpu clock control e enables energy efficient desktop systems y only available as part of a supported kit y 208-pin qfp package
82374eb/82374SB this document describes both the 82374eb and 82374SB components. unshaded areas describe the 82374eb. shaded areas, like this one, describe the 82374SB operations that differ from the 82374eb. the 82374eb/sb eisa system component (esc) provides all the eisa system compatible functions. the esc with the pceb provide all the functions to implement an eisa-to-pci bridge and eisa i/o subsystem. the esc integrates the common i/o functions found in today's eisa-based pc systems. the esc incorp- orates the logic for an eisa (master and slave) interface, eisa bus controller, enhanced seven channel dma controller with scatter-gather support, eisa arbitration, 14 channel interrupt controller, advanced programma- ble interrupt controller (apic), five programmable timer/counters, and non-maskable-interrupt (nmi) control logic. the esc also integrates support logic to decode peripheral devices such as the flash bios, real time clock, keyboard/mouse controller, floppy controller, two serial ports, one parallel port, and ide hard disk drive. the 82374SB also contains support for smm power management 2
82374eb/82374SB 290476 1 note: smm interface and init are on the 82347sb only. simplified esc block diagram 3
82374eb/82374SB eisa system component (esc) contents page 1.0 architectural overview 11 1.1 pceb overview 14 1.2 esc overview 16 2.0 signal description 17 2.1 pci local bus interface signals 18 2.2 eisa bus interface signals 18 2.3 isa bus signals 21 2.4 dma signal description 24 2.5 eisa arbitration signals 25 2.6 timer unit signal 26 2.7 interrupt controller signals 27 2.8 apic bus signals 27 2.9 system power management signals (82374SB only) 27 2.10 esc/pceb interface signals 28 2.10.1 arbitration and interrupt acknowledge control 28 2.10.2 pceb buffer coherency control 29 2.11 integrated logic signals 30 2.11.1 eisa address buffer control 30 2.11.2 coprocessor interface 30 2.11.3 bios interface 30 2.11.4 keyboard controller interface 31 2.11.5 real time clock interface 31 2 11.6 floppy disk controller interface 32 2.11.7 configuration ram interface 33 2.11.8 x-bus control and general purpose decode 33 2.12 test signal 35 3.0 register description 35 3.1 configuration registers 35 3.1.1 escideesc id register 36 3.1.2 riderevision id register 36 3.1.3 msemode select register 36 3.1.4 bioscsaebios chip select a register 38 3.1.5 bioscsbebios chip select b register 39 4
contents page 3.1.6 clkdiveeisa clock divisor register 40 3.1.7 pcsaeperipheral chip select a register 41 3.1.8 pcsbeperipheral chip select b register 42 3.1.9 eisaid [ 4:1 ] eeisa id registers 43 3.1.10 sgrbaescatter/gather relocate base address register 43 3.1.11 apicbaseeapic base address relocation 44 3.1.12 pirq [ 0:3 ] y epirq route control registers 44 3.1.13 gpcsla [ 2:0 ] egeneral purpose chip select low address register 45 3.1.14 gpcsha [ 2:0 ] egeneral purpose chip select high address register 45 3.1.15 gpcsm [ 2:0 ] egeneral purpose chip select mask register 46 3.1.16 gpxbcegeneral purpose peripheral x-bus control register 46 3.1.17 pacepci/apic control register 47 3.1.18 testcetest control register 47 3.1.19 smicntlesmi control register 47 3.1.20 smienesmi enable register 48 3.1.21 seeesystem event enable register 49 3.1.22 ftmrefast off timer register 50 3.1.23 smireqesmi request register 50 3.1.24 ctltmreclock scale stpclk y low timer 52 3.1.25 ctltmrheclock scale stpclk y high timer 52 3.2 dma register description 52 3.2.1 dcomecommand register 52 3.2.2 dcmedma channel mode register 54 3.2.3 dcemedma channel extended mode register 55 3.2.4 dredma request register 58 3.2.5 mask registerewrite single mask bit 58 3.2.6 wambewrite all mask bits register 59 3.2.7 dsedma status register 60 3.2.8 db&caedma base and current address register (8237 compatible segment) 61 3.2.9 db&cbwedma base and current byte/word count register (8237 compatible segment) 62 3.2.10 dma base and current high byte/word count register; dma base high byte/word count register 63 3.2.11 dma memory low page register; dma memory base low page register 64 3.2.12 dmapedma page register 64 5
contents page 3.2.13 dmalpredma low page refresh register 65 3.2.14 dmamhpgedma memory high page register; dma memory base high page register 65 3.2.15 dmahpgredma high page register refresh 66 3.2.16 stop registers 66 3.2.17 chainechaining mode register 67 3.2.18 chainstaechaining mode status register 68 3.2.19 chintstechannel interrupt status register 68 3.2.20 chainbecechain buffer expiration control register 68 3.2.21 scatgaescatter-gather command register 69 3.2.22 scagastescatter-gather status register 71 3.2.23 scagadescatter-gather descriptor table pointer register 72 3.2.24 cbpffeclear byte pointer flip flop register 73 3.2.25 dmcedma master clear register 73 3.2.26 dcmedma clear mask register 74 3.3 timer unit registers 74 3.3.1 tcwetimer control word register 74 3.3.2 timer read back command register 76 3.3.3 counter latch command register 77 3.3.4 tmstatetimer status byte format register 78 3.3.5 capsecounter access ports 79 3.4 interrupt controller registers 79 3.4.1 icw1einitialization command word 1 79 3.4 2 icw2einitialization command word 2 81 3.4.3 icw3einitialization command word 3 (master) 82 3.4.4 icw3einitialization command word 3 (slave) 82 3.4.5 icw4einitialization command word 4 83 3.4.6 ocw1eoperation control word 1 84 3.4.7 ocw2eoperation control word 2 84 3.4.8 ocw3eoperation control word 3 85 3.4.9 elcreedge/level control register 87 3.4.10 nmiscenmi status and control register 87 3.4.11 nmiertcenmi control and real-time clock address 88 3.4.12 nmiescenmi extended status and control register 89 3.4.13 softnmiesoftware nmi generation register 90 3.5 eisa configuration, floppy support, and port 92h 90 3.5.1 conframpeconfiguration ram page register 90 3.5.2 digoutedigital output register 90 6
contents page 3.5.3 port 92 register 91 3.5.4 leisamgelast eisa bus master granted register 92 3.6 power management registers 92 3.6.1 apmceadvanced power management control port 92 3.6.2 apmseadvanced power management status port 92 3.7 apic registers 93 3.7.1 ioregselei/o register select register 93 3.7.2 iowinei/o window register 93 3.7.3 apicidei/o apic identification register 94 3.7.4 apicidei/o apic identification register 94 3.7.5 apicarbei/o apic arbitration register 95 3.7.6 ioredtbl [ 15:0 ] ei/o redirection table registers 95 4.0 address decoding 98 4.1 bios memory space 98 4.2 i/o addresses contained within the esc 101 4.3 configuration addresses 110 4.4 x-bus peripherals 112 4.5 i/o apic registers 114 5.0 eisa controller functional description 115 5.1 overview 115 5.2 clock generation 116 5.2.1 clock stretching 116 5.3 eisa master cycles 117 5.3.1 eisa master to 32-bit eisa slave 117 5.3.2 eisa master to 16-bit isa slave 119 5.3.3 eisa master to 8-bit eisa/isa slaves 119 5.3.4 eisa master back-off 120 5.4 isa master cycles 121 5.4.1 isa master to 32-/16-bit eisa slave 121 5.4.2 isa master to 16-bit isa slave 121 5.4.3 isa master to 8-bit eisa/isa slave 123 5.4.4 isa wait state generation 123 5.5 mis-match cycles 124 5.6 data swap buffer control logic 125 5.7 servicing dma cycles 126 5.8 refresh cycles 126 7
contents page 5.9 eisa slot support 126 5.9.1 aen generation 126 5.9.2 mackx y generation 128 6.0 dma controller 128 6.1 dma controller overview 128 6.2 dma transfer modes 130 6.2.1 single transfer mode 130 6.2.2 block transfer mode 130 6.2.3 demand transfer mode 130 6.2.4 cascade mode 131 6.3 dma transfer types 131 6.4 dma timing 131 6.4.1 compatible timings 132 6.4.2 type ``a'' timing 133 6.4.3 type ``b'' timing 134 6.4.4 type ``c'' (burst) timing 135 6.5 channel priority 135 6.6 scatter-gather functional description 136 6.7 register functionality 138 6.7.1 address compatibility mode 138 6.7.2 summary of the dma transfer sizes 139 6.7.3 address shifting when programmed for 16-bit i/o count by words 139 6.7.4 stop registers (ring buffer data structure) 139 6.7.5 buffer chaining mode and status registers 140 6.7.6 autoinitialize 141 6.8 software commands 141 6.8.1 clear byte pointer flip-flop 141 6.8.2 dma master clear 141 6.8.3 clear mask register 141 6.9 terminal count/eop summary 142 6.10 buffer chaining 142 6.11 refresh unit 143 7.0 eisa bus arbitration 143 7.1 arbitration priority 144 7.2 preemption 144 7.2.1 pceb eisa bus acquisition and pceb preemption 144 8
contents page 7.2.2 eisa master preemption 146 7.2.3 dma preemption 146 7.3 slave timeouts 146 7.4 arbitration during non-maskable interrupts 146 8.0 interval timers 146 8.1 interval timer address map 147 8.2 programming the interval timer 148 9.0 interrupt controller 151 9.1 interrupt controller internal registers 153 9.2 interrupt sequence 153 9.3 80x86 mode 154 9.3.1 esc interrupt acknowledge cycle 154 9.4 programming the interrupt controller 155 9.5 end-of-interrupt operation 158 9.5.1 end of interrupt (eoi) 158 9.5.2 automatic end of interrupt (aeoi) mode 159 9.6 modes of operation 159 9.6.1 fully nested mode 159 9.6.2 the special fully nested mode 160 9.6.3 automatic rotation (equal priority devices) 160 9.6.4 specific rotation (specific priority) 161 9.6.5 poll command 161 9.6.6 cascade mode 161 9.6.7 edge and level triggered modes 162 9.7 register functionality 162 9.7.1 initialization command words 162 9.7.2 operation control words (ocws) 163 9.8 interrupt masks 163 9.8.1 masking on an individual interrupt request basis 163 9.8.2 special mask mode 163 9.9 reading the interrupt controller status 163 9.10 non-maskable interrupt (nmi) 164 10.0 advanced programmable interrupt controller (apic) 166 10.1 physical characteristics of apic bus 168 10.2 arbitration for apic bus 168 10.3 bus message formats 169 9
contents page 11.0 pceb/esc interface 176 11.1 arbitration control signals 176 11.2 system buffer coherency controleapic 178 11.3 power management 178 11.4 eisa data swap buffer control signals 178 11.5 interrupt acknowledge control 179 12.0 integrated support logic 180 12.1 eisa address buffer control 180 12.2 coprocessor interface 181 12.3 bios interface 182 12.4 keyboard controller interface 182 12.5 real time clock 183 12.6 floppy disk control interface 183 12.7 configuration ram interface 184 12.8 general purpose peripherals, ide, parallel port, and serial port interface 184 12.9 x-bus control and general purpose decode 185 13.0 power management (82374SB) 187 13.1 smm mode 188 13.2 smi sources 188 13.3 smi y and init interaction 189 13.3.1 clock control 189 13.4 stop grant special cycle 191 13.5 dual-processor power management support 191 13.5.1 smi y delivery mechanism 191 13.5.2 stpclk y tied to both sockets 192 13.5.3 smi y /intr (apic mode) 192 14.0 electrical characteristics 192 14.1 maximum ratings 192 14.2 nand tree 192 15.0 pinout and package information 199 15.1 pinout and pin assignment 199 15.2 package characteristics 208 10
82374eb/82374SB 1.0 architectural overview the pci-eisa bridge chip set provides an i/o subsystem core for the next generation of high-performance personal computers (e.g., those based on the intel486 tm or pentium processors). system designers can take advantage of the power of the pci (peripheral component interconnect) for the local i/o bus while maintain- ing access to the large base of eisa and isa expansion cards, and corresponding software applications. extensive buffering and buffer management within the pci-eisa bridge ensures maximum efficiency in both bus environments. the chip set consists of two componentsethe 82375eb/sb pci-eisa bridge (pceb) and the 82374eb/sb eisa system component (esc). these components work in tandem to provide an eisa i/o subsystem interface for personal computer platforms based on the pci standard. this section provides an overview of the pci and eisa bus hierarchy followed by an overview of the pceb and esc components. bus hierarchyeconcurrent operations: figure 1 shows a block diagram of a typical system using the pci-eisa bridge chip set. the system contains three levels of buses structured in the following hierarchy: # host bus as the execution bus # pci bus as a primary i/o bus # eisa bus as a secondary i/o bus this bus hierarchy allows concurrency for simultaneous operations on all three bus environments. data buffer- ing permits concurrency for operations that cross over into another bus environment. for example, a pci device could post data into the pceb, permitting the pci local bus transaction to complete in a minimum time and freeing up the pci local bus for further transactions. the pci device does not have to wait for the transfer to complete to its final destination. meanwhile, any ongoing eisa bus transactions are permitted to complete. the posted data is then transferred to its eisa bus destination when the eisa bus is available. the pci-eisa bridge chip set implements extensive buffering for pci-to-eisa and eisa-to-pci bus transactions. in addition to concurrency for the operations that cross bus environments, data buffering allows the fastest operations within a particular bus environment (via pci burst transfers and eisa burst transfers). the pci local bus with 132 mbyte/sec and eisa with 33 mbyte/sec peak data transfer rate represent bus environments with significantly different bandwidths. without buffering, transfers that cross the single bus environment are performed at the speed of the slower bus. data buffers provide a mechanism for data rate adoption so that the operation of the fast bus environment (pci), i.e. usable bandwidth, is not significantly impacted by the slower bus environment (eisa). 11
82374eb/82374SB 290476 2 figure 1. pci-eisa chip set system block diagram 12
82374eb/82374SB pci bus the pci bus has been defined to address the growing industry needs for a standardized local bus that is not directly dependent on the speed and the size of the processor bus. new generations of personal computer system software such as windows tm and win-nt tm with sophisticated graphical interfaces, multi-tasking and multi-threading bring new requirements that traditional pc i/o architectures can not satisfy. in addition to the higher bandwidth, reliability and robustness of the i/o subsystem is becoming increasingly important. the pci environment addresses these needs and provides an upgrade path for the future. pci features include: # processor independent # multiplexed, burst mode operation # synchronous at frequencies from 20 33 mhz # 120 mbyte/sec usable throughput (132 mbyte/sec peak) for 32 bit data path # 240 mbyte/sec usable throughput (264 mbyte/sec peak) for 64 bit data path # optional 64 bit data path with operations that are transparent with the 32 bit data path # low latency random access (60 ns write access latency to slave registers from a master parked on the bus) # capable of full concurrency with processor/memory subsystem # full multi-master capability allowing any pci master peer-to-peer access to any pci slave # hidden (overlapped) central arbitration # low pin count for cost effective component packaging (address/data multiplexed) # address and data parity # three physical address spaces: memory, i/o, and configuration # comprehensive support for autoconfiguration through a defined set of standard configuration functions system partitioning shown in figure 1 illustrates how the pci can be used as a common interface between different portions of a system platform that are typically supplied by the chip set vendor. these portions are the host/pci bridge (including a main memory dram controller and an optional second level cache controller) and the pci-eisa bridge. thus, the pci allows a system i/o core design to be decoupled from the processor/ memory treadmill, enabling the i/o core to provide maximum benefit over multiple generations of processor/ memory technology. for this reason, the pci-eisa bridge can be used with different processors. regardless of the new requirements imposed on the processor side of the host/pci bridge (e.g. 64-bit data path, 3.3v interface, etc.) the pci side remains unchanged which allows reusability not only of the rest of the platform chip set (i.e. pci-eisa bridge) but also of all other i/o functions interfaced at the pci level. these functions typically include graphics, scsi, and lan. eisa bus the eisa bus in the system shown in the figure 1.0 represents a second level i/o bus. it allows personal computer platforms built around the pci as a primary i/o bus to leverage the large eisa/isa product base. combinations of pci and eisa buses, both of which can be used to provide expansion functions, will satisfy even the most demanding applications. along with compatibility with 16-bit and 8-bit isa hardware and software, the eisa bus provides the following key features: # 32-bit addressing and 32-bit data path # 33 mbyte/sec bus bandwidth # multiple bus master support through efficient arbitration # support for autoconfiguration 13
82374eb/82374SB integrated bus central control functions the pci-eisa bridge chip set integrates central bus functions on both the pci and eisa buses. for the pci bus, the functions include pci bus arbitration and default bus driver. for the eisa bus, central functions include the eisa bus controller and eisa arbiter are integrated in the esc component and eisa data swap logic is integrated in the pceb. integrated system functions the pci-eisa bridge chip set integrates system functions including pci parity and system errors reporting, buffer coherency management protocol, pci and eisa memory and i/o address space mapping and decod- ing. for maximum flexibility all of these functions are programmable allowing for variety of optional features. 1.1 pceb overview the pceb provides the interface (bridge) between pci and eisa buses by translating bus protocols in both directions. it uses extensive buffering on both the pci and eisa interfaces to allow concurrent bus operations. the pceb also implements the pci central support functions (e.g., pci arbitration, error signal support, and subtractive decoding). the major functions provided by the pceb are described in this section. pci bus interface the pceb can be either a master or slave on the pci bus and supports bus frequencies from 25 mhz to 33 mhz. for pci-initiated transfers, the pceb can only be a slave. the pceb becomes a slave when it positively decodes the cycle. the pceb also becomes a slave for unclaimed cycles on the pci bus. these unclaimed cycles are either negatively or subtractively decoded by the pceb and forwarded to the eisa bus. as a slave, the pceb supports single cycle transfers for memory, i/o, and configuration operations and burst cycles for memory operations. note that, burst transfers cannot be performed to the pceb's internal registers. burst memory write cycles to the eisa bus can transfer up to four dwords, depending on available space in the pceb's posted write buffers. when space is no longer available in the buffers, the pceb terminates the transaction. this supports the incremental latency mechanism as defined in the peripheral component inter- connect (pci) specification. note that, if the posted write buffers are disabled, pci burst operations are not performed and all transfers are single cycle. for eisa-initiated transfers to the pci bus, the pceb is a pci master. the pceb permits eisa devices to access either pci memory or i/o. while all pci i/o transfers are single cycle, pci memory cycles can be either single cycle or burst, depending on the status of the pceb's line buffers. during eisa reads of pci memory, the pceb uses a burst read cycle of four dwords to prefetch data into a line buffer. during eisa-to- pci memory writes, the pceb uses pci burst cycles to flush the line buffers. the pceb contains a program- mable master latency timer that provides the pceb with a guaranteed time slice on the pci bus, after which it surrenders the bus. as a master on the pci bus, the pceb generates address and command signal (c/be y ) parity for read and write cycles, and data parity for write cycles. as a slave, the pceb generates data parity for read cycles. parity checking is not supported. the pceb, as a resource, can be locked by any pci master. in the context of locked cycles, the entire pceb subsystem (including the eisa bus) is considered a single resource. 14
82374eb/82374SB pci bus arbitration the pci arbiter supports six pci mastersethe host/pci bridge, pceb, and four other pci masters. the arbiter can be programmed for twelve fixed priority schemes, a rotating scheme, or a combination of the fixed and rotating schemes. the arbiter can be programmed for bus parking that permits the host/pci bridge default access to the pci bus when no other device is requesting service. the arbiter also contains an efficient pci retry mechanism to minimize pci bus thrashing when the pceb generates a retry. the arbiter can be disabled, if an external arbiter is used. eisa bus interface the pceb contains a fully eisa-compatible master and slave interface. the pceb directly drives eight eisa slots without external data or address buffering. the pceb is only a master or slave on the eisa bus for transfers between the eisa bus and pci bus. for transfers contained to the eisa bus, the pceb is never a master or slave. however, the data swap logic contained in the pceb is involved in these transfers, if data size translation is needed. the pceb also provide support for i/o recovery. eisa/isa masters and dma can access pci memory or i/o. the pceb only forwards eisa cycles to the pci bus if the address of the transfer matches one of the address ranges programmed into the pceb for eisa-to- pci positive decode. this includes the main memory segments used for generating memcs y from the eisa bus, one of the four programmable memory regions, or one of the four programmable i/o regions. for eisa- initiated accesses to the pci bus, the pceb is a slave on the eisa bus. i/o accesses are always non-buffered and memory accesses can be either non-buffered or buffered via the line buffers. for buffered accesses, burst cycles are supported. during pci-initiated cycles to the eisa bus, the pceb is an eisa master. for memory write operations through the posted write buffers, the pceb uses eisa burst transfers, if supported by the slave, to flush the buffers. otherwise, single cycle transfers are used. single cycle transfers are used for all i/o cycles and memory reads. pci/eisa address decoding the pceb contains two address decoderseone to decode pci-initiated cycles and the other to decode eisa- initiated cycles. the two decoders permit the pci and eisa buses to operate concurrently. the pceb can also be programmed to provide main memory address decoding on behalf of the host/pci bridge. when programmed, the pceb monitors the pci and eisa bus cycle addresses, and generates a memory chip select signal (memcs y ) indicating that the current cycle is targeted to main memory residing behind the host/pci bridge. programmable features include, read/write attributes for specific memory seg- ments and the enabling/disabling of a memory hole. if memcs y is not used, this feature can be disabled. in addition to the main memory address decoding, there are four programmable memory regions and four programmable i/o regions for eisa-initiated cycles. eisa/isa master or dma accesses to one of these regions are forwarded to the pci bus. data buffering to isolate the slower eisa bus from the pci bus, the pceb provides two types of data buffers. buffer management control guarantees data coherency. for eisa-initiated cycles to the pci bus, there are four 16-byte wide line buffers. these buffers permit prefetching of pci memory read data and posting of pci memory write data. 15
82374eb/82374SB by using burst transactions to fill or flush these buffers, if appropriate, the pceb maximizes bus efficiency. for example, an eisa device could fill a line buffer with byte, word, or dword transfers and the pceb would use a pci burst cycle to flush the filled line to pci memory. bios timer the pceb has a 16 bit bios timer. the timer can be used by bios software to implement timing loops. the timer count rate is derived from the eisa clock (bclk) and has an accuracy of g 1 m s. 1.2 esc overview the esc implements system functions (e.g., timer/counter, dma, and interrupt controller) and eisa subsys- tem control functions (e.g., eisa bus controller and eisa bus arbiter). the major functions provided by the esc are described in this section. eisa controller the esc incorporates a 32-bit master and an 8-bit slave. the esc directly drives eight eisa slots without external data or address buffering. eisa system clock (bclk) generation is integrated by dividing the pci clock (divide by 3 or divide by 4) and wait-state generation is provided. the aenx and mackx signals provide a direct interface to four eisa slots and supports eight eisa slots with encoded aenx and mackx signals. the esc contains an 8-bit data bus (lower 8 bits of the eisa data bus) that is used to program the esc's internal registers. note that for transfers between the pci and eisa buses, the pceb provides the data path. thus, the esc does not require a full 32 bit data bus. a full 32-bit address bus is provided and is used during refresh cycles and for dma operations. the esc performs cycle translation between the eisa bus and isa bus. for mis-matched master/slave combinations, the esc controls the data swap logic that is located in the pceb. this control is provided through the pceb/esc interface. dma controller the esc incorporates the functionality of two 82c37 dma controllers with seven independently programma- ble channels. each channel can be programmed for 8 or 16 bit dma device size, and isa-compatible, type ``a'', type ``b'', or type ``c'' timings. full 32 bit addressing is provided. the dma controller is also responsible for generating refresh cycles. the dma controller supports an enhanced feature called scatter/gather. this feature provides the capability of transferring multiple buffers between memory and i/o without cpu intervention. in scatter/gather mode, the dma can read the memory address and word count from an array of buffer descriptors, located in main memory, called the scatter/gather descriptor (sgd) table. this allows the dma controller to sustain dma transfers until all of the buffers in the sgd table are handled. interrupt controller the esc contains an eisa compatible interrupt controller that incorporates the functionality of two 82c59 interrupt controllers. the two interrupt controllers are cascaded providing 14 external and two internal inter- rupts. 16
82374eb/82374SB advanced programmable interrupt controller (apic) in addition to the standard eisa compatible interrupt controller described above, the esc incorporates the advanced programmable interrupt controller (apic). while the standard interrupt controller is intended for use in a uni-processor system, apic can be used in either a uni-processor or multi-processor system. apic provides multi-processor interrupt management and incorporates both static and dynamic symmetric interrupt distribution across all processors. in systems with multiple i/o subsystems, each subsystem can have its own set of interrupts. timer/counter the esc provides two 82c54 compatible timers (timer 1 and timer 2). the counters in timer 1 support the system timer interrupt (irq0 y ), refresh request, and a speaker tone output (spkr). the counters in timer 2 support fail-safe timeout functions and the cpu speed control. integrated support logic to minimize the chip count for board designs, the esc incorporates a number of extended features. the esc provides support for alta20 (fast a20gate) and altrst with i/o port 92h. the esc generates the control signals for sa address buffers and x-bus buffer. the esc also provides chip selects for bios, the keyboard controller, the floppy disk controller, and three general purpose devices. support for generating chip selects with an external decoder is provided for ide, a parallel port, and a serial port. the esc provides support for a pc/at compatible coprocessor interface and irq13 generation. power management (82374SB) extensive power management capability permits a system to operate in a low power state without being powered down. once in the low power state (called ``fast off'' state), the computer appears to be off. for example, the smm code could turn off the crt, line printer, hard disk drive's spindle motor, and fans. in addition, the cpu's clock can be governed. to the user, the machine appears to be in the off state. however, the system is actually in an extremely low power state that still permits the cpu to function and maintain communication connections normally associated with today's desktops (e.g., lan, modem, or fax). program- mable options provide power management flexibility. for example, various system events can be programmed to place the system in the low power state or break events can be programmed to wake the system up. 2.0 signal description this section provides a detailed description of each signal. the signals are arranged in a functional group according to their associated interface. the `` y '' symbol at the end of a signal indicates that the active, or asserted state occurs when the signal is at a low voltage level. when `` y '' is not presented after the signal name, the signal is asserted when at the high voltage level. the terms assertion and negation are used extensively. this is done to avoid confusion when working with a mixture of ``active-low'' and ``active-high'' signals. the term assert ,or assertion indicates that a signal is active, independent of whether that level is represented by a high or low voltage. the term negate ,or negation indicates that a signal is inactive. 17
82374eb/82374SB the following notations are used to describe the signal type. in input is a standard input-only signal. out totem pole output is a standard active driver. o/d open drain input/output. t/s tri-state is a bi-directional, tri-state input/output pin. s/t/s sustained tri-state is an active low tri-state signal owned and driven by one and only one agent at a time. the agent that drives a s/t/s pin low must drive it high for at least one clock before letting it float. a new agent can not start driving a s/t/s signal any sooner than one clock after the previous owner tri- states it. a pull-up sustains the inactive state until another agent drives it and is provided by the central resource. note: during a hard reset, intr, nmi, ignne y , smi y (on 82374SB), altrst y , stpclk y (on 82374SB) and alta20 are driven low to prevent problems associated with 5v/3.3v power sequencing. any outputs of the esc that are directed to a 3.3v cpu must be driven through a 5v to 3.3v translator. 2.1 pci local bus interface signals pin name type description pciclk in pci clock: pciclk provides timing for all transactions on the pci bus. the esc uses the pci clock (pciclk) to generate eisa bus clock (bclk). the pciclk is divided by 3 or 4 to generate the bclk. the eisa bridge supports pci clock frequencies of 25 mhz through 33 mhz. perr y in parity error: perr y indicates a data parity error. perr y may be pulsed active by any agent that detects an error condition. upon sampling perr y active, the esc generates an nmi interrupt to the cpu. serr y in system error: serr y may be pulsed active by any agent that detects an error condition. upon sampling serr y active, the esc generates an nmi interrupt to the cpu. reset y in system reset: reset y forces the entire esc chip into a known state. all internal esc state machines are reset and all registers are set to their default values. reset y may be asynchronous to pciclk when asserted or negated. although asynchronous, negation must be a clean, bounce-free edge. the esc uses reset y to generate rstdrv signal. 2.2 eisa bus interface signals pin name type description bclkout out eisa bus clock output : bclkout is typically buffered to create eisa bus clock (bclk). the bclk is the system clock used to synchronize events on the eisa/isa bus. the bclkout is generated by dividing the pciclk. the esc uses a divide by 3 or divide by 4 to generate the bclkout. bclk in eisa bus clock : the esc uses bclk to synchronize events on the eisa bus. the esc generates or samples all the eisa/isa bus signals on either the rising or the falling edge of bclk. 18
82374eb/82374SB pin name type description la [ 31:27 ] y / t/s eisa address bus/configuration ram page address : these are multiplexed signals. these signals behave as the eisa address bus under all cpg [ 4:0 ] conditions except during access cycle to the configuration ram. eisa address bus: la [ 31:27 ] y are directly connected to the eisa address bus. the esc uses the address bus in conjunction with the be [ 3:0 ] y signals as inputs to decode accesses to its internal resources except in dma and refresh modes. during dma and refresh modes, these are outputs, and the esc uses these signals in conjunction with be [ 3:0 ] y to drive memory address. configuration ram page address: cpg [ 4:0 ] are connected to configuration sram address lines. during i/o access to 0800h-08ffh, the esc drives these signals with the configuration page address (the value contained in register 0c00h). the configuration ram page address function can be disabled by setting mode select register bit 5 e 0. la [ 26:24 ] y t/s eisa address bus : these signals are directly connected to the eisa address bus. the esc uses the address bus in conjunction with the be [ 3:0 ] y signals as and inputs to decode accesses to its internal resources except in dma and refresh la [ 23:2 ] modes. during dma and refresh modes, these are outputs, and the esc uses these signals in conjunction with be [ 3:0 ] y to drive memory address. be [ 3:0 ] y t/s byte enables :be [ 3:0 ] y signals are directly connected to the eisa address bus. these signals indicate which byte on the 32-bit eisa data bus are involved in the current cycle. be [ 3:0 ] y are inputs during eisa master cycles which do not require assembly/disassembly operation. for eisa master assembly/disassembly cycles, isa master cycles, dma, and refresh cycles be [ 3:0 ] y are outputs. be0 y : corresponds to byte lane 0-sd [ 7:0 ] be1 y : corresponds to byte lane 0-sd [ 15:8 ] be2 y : corresponds to byte lane 0-sd [ 23:16 ] be3 y : corresponds to byte lane 0-sd [ 31:24 ] m/io y t/s memory or i/o cycle: m/io y signal is used to differentiate between memory cycles and i/o cycles on the eisa bus. a high value on this signal indicates a memory cycle, and a low value indicates an i/o cycle. m/io y is an input to the esc during eisa master cycles, and m/io y is an output during isa, dma, and esc initiated refresh cycles. m/io y is floated during isa master initiated refresh cycles. w/r y t/s write or read cycle: w/r y signal is used to differentiate between write and read cycles on the eisa bus. a high value on this signal indicates a write cycle , and a low value indicates a read cycle. w/r y is an input to the esc during eisa master cycles, and w/r y is an output during isa, dma, and refresh cycles. 19
82374eb/82374SB pin name type description ex32 y o/d eisa 32 bit device decode : ex32 y signal is asserted by a 32-bit eisa slave device. ex32 y assertion indicates that an eisa device has been selected as a slave, and the device has a 32-bit data bus size. the esc uses this signal as an input as part of its slave decode to determine if data size translation and/or cycle translation is required. ex32 y is an output of the esc during the last portion of the mis-matched cycle. this is an indication to the backed-off eisa master that the data translation has been completed. the backed-off eisa master uses this signal to start driving the eisa bus again. ex16 y o/d eisa 16-bit device decode: ex16 y signal is asserted by a 16-bit eisa slave device. ex16 y assertion indicates that an eisa device has been selected as a slave, and the device has a 16 bit data bus size. the esc uses this signal as an input as part of its slave decode to determine if data size translation and/or cycle translation is required. ex16 y is an output of the esc during the last portion of the mis-matched cycle. this is an indication to the backed-off eisa master that the data translation has been completed. the backed-off eisa master uses this signal to start driving the eisa bus again. start y t/s start cycle: start y signal provides timing control at the start of an eisa cycle. start y is asserted for one bclk. start y is an input to the esc during eisa master cycles except portions of the eisa master to mis-matched slave cycles where it becomes an output. during isa, dma, and refresh cycles start y is an output. cmd y out command: cmd y signal provides timing control within an eisa cycle. the esc is a central resource of the cmd y signal, and the esc generates cmd y during all eisa cycles. cmd y is asserted from the rising edge of bclk simultaneously with the negation of start y , and remains asserted until the end of the cycle. exrdy o/d eisa ready: exrdy signal is deasserted by eisa slave devices to add wait states to a cycle. exrdy is an input to the esc for eisa master cycles, isa master cycles, and dma cycles where an eisa slave has responded with ex32 y or ex16 y asserted. the esc samples exrdy on the falling edge of bclk after cmd y is asserted (except during dma compatible cycles). during dma compatible cycles, exrdy is sampled on the second falling edge of bclk after cmd y is driven active. for all types of cycles if exrdy is sampled inactive, the esc keeps sampling it on every falling edge of bclk y . exrdy is an output for eisa master cycles decoded as accesses to the esc internal registers. esc forces exrdy low for one bclk at the start of a potential dma burst write cycle to insure that the initial write data is held long enough to be sampled by the memory slave. slburst y in slave burst: slburst y signal is asserted by an eisa slave to indicate that the device is capable of accepting eisa burst cycles. the esc samples slburst y on the rising edge of bclk at the end of start y for all eisa cycles. during dma cycles, the esc samples slburst y twice; once on the rising edge of bclk at the beginning of start y and again on the rising edge of bclk at the end of start y . 20
82374eb/82374SB pin name type description msburst y t/s master burst: msburst y signal is asserted by an eisa master to indicate eisa burst cycles. msburst y is asserted by an eisa master in response to an asserted slburst y signal. the esc samples slburst y on the rising edge of bclk that cmd y is asserted. if asserted, the esc samples slburst y on all subsequent rising edges of bclk until sampled negated. the esc keeps cmd y asserted during burst cycles. msburst y is an output during dma burst cycles. the esc drives msburst y active on the falling edge of bclk, one half bclk after slburst y is sampled active at the end of start y . master16 y in master 16-bit: master16 y is asserted by a 16-bit eisa bus master or an isa bus master device to indicate that it has control of the eisa bus or isa bus. the esc samples master16 y on the rising edge of bclk that start y is asserted. if master16 y is sampled asserted, the esc determines that a 16-bit eisa bus master or an isa bus master owns the bus. if master16 y is sampled negated at the first sampling point, the esc will sample master16 y a second time on the rising edge of bclk at the end of start y . if master16 y is sampled asserted here, the esc determines that a 32-bit eisa bus master has downshifted to a 16-bit bus master, and thus, the esc will disable the data size translation function. sd [ 7:0 ] t/s system data: sd [ 7:0 ] signals are directly connected to the system data bus. the sd [ 7:0 ] pins are outputs during i/o reads when the esc internal registers are being accessed and during interrupt acknowledge cycles. the sd [ 7:0 ] pins are input during i/o writes cycles when the esc internal registers are being accessed. 2.3 isa bus signals pin name type description bale out bus address latch enable: bale signal is asserted by the esc to indicate that a address (sa [ 19:0 ] ,la [ 23:17 ] ), aen and sbhe y signal lines are valid. the la [ 23:17 ] address lines are latched on the trailing edge of bale. bale remains active throughout dma and isa master cycles and refresh cycles. sa [ 1:0 ] t/s isa address bits 0& 1: sa [ 1:0 ] are the least significant bits of the isa address bus. sa [ 1:0 ] are inputs to the esc during isa master cycles except during isa master initiated refresh cycles. the esc uses the sa [ 1:0 ] in conjunction with sbhe y to generate be [ 3:0 ] y on the eisa bus. the sa [ 1:0 ] are outputs of the esc during eisa master cycles and dma cycles. the esc generates these from be [ 3:0 ] y . sbhe y t/s isa byte high enable: sbhe y signal indicates that the high byte on the isa data bus (sd [ 15:8 ] ) is valid. sbhe y is an input to the esc during isa master cycles, except during isa master initiated refresh cycles. the esc uses the sbhe y in conjunction with sa [ 1:0 ] to generate be [ 3:0 ] y on the eisa bus. sbhe y is an output during eisa master and dma cycles. 21
82374eb/82374SB pin name type description m16 y o/d memory chip select 16: m16 y is an input when the esc component owns the isa bus. m16 y is an output when an external isa bus master owns the isa bus. the isa slave memory drives this signal low if it is a 16-bit memory device. for isa to eisa translation cycles, the esc combinatorially asserts m16 y if either ex32 y or ex16 y are asserted. this signal has an external pull-up resistor. io16 y o/d 16 bit i/o chip select: io16 y signal is used to indicate a 16-bit i/o bus cycle. this signal is asserted by the i/o devices to indicate that they support 16-bit i/o bus cycles. all i/o accesses to the esc registers are run as 8-bit i/o bus cycles. this signal has an external pull-up resistor. mrdc y t/s memory read: mrdc y signal indicates a read cycle to the isa memory devices. mrdc y is the command to a memory slave that it may drive data onto the isa data bus. mrdc y is an output when the esc owns the isa bus. mrdc y is an input when an external isa bus master owns the isa bus. this signal is driven by the esc during refresh cycles. mwtc y t/s memory write: mwtc y signal indicates a write cycle to the isa memory devices. mwtc y is the command to a memory slave that it may latch data from the isa data bus. mwtc y is an output when the esc owns the isa bus. mwtc y is an input when an isa bus master owns the isa bus. smrdc y out system memory read: smrdc y signal is asserted by the esc to request a memory slave to drive data onto the data lines. smrdc y indicates that the memory read cycle is for an address below the 1 mbyte range on the isa bus. this signal is also asserted during refresh cycles. smwtc y out system memory write: smwtc y signal is asserted by the esc to request a memory slave to accept data from the data lines. smwtc y indicates that the memory write cycle is for an address below the 1 mbyte range. iorc y t/s i/o read: iorc y is the command to an isa i/o slave device that it may drive data on to the data bus (sd [ 15:0 ] ). the device must hold the data valid until after iorc y is negated. iorc y is an output when the esc component owns the isa bus. iorc y is an input when an isa bus master owns the isa bus. iowc y t/s i/o write: iowc y is the command to an isa i/o slave device that it may latch data from the isa data bus (sd [ 15:0 ] ). iowc y is an output when the esc component owns the isa bus. iowc y is an input when an isa bus master owns the isa bus. chrdy o/d i/o channel ready: chrdy when asserted allows isa bus resources request additional time (wait-states) to complete the cycle. chrdy is an input when the esc owns the isa bus. chrdy is an input to the esc during compatible dma cycles. chrdy is an output during isa bus master cycles to pci slave or esc internal register. the esc will ignores chrdy for isa-bus master accessing an isa-bus slave. iochk y in i/o channel check: iochk y can be asserted by any resource on the isa bus. when asserted, it indicates that a parity or an uncorrectable error has occurred for a device or memory on the isa bus. a nmi will be generated to the cpu if enabled. 22
82374eb/82374SB pin name type description nows y o/d zero wait states: nows y indicates that an peripheral device wishes to execute a zero wait-state bus cycle (the normal default 16-bit isa bus memory or i/o cycle is 3 bclks). when nows y is asserted, a 16-bit memory cycle will occur in two bclks and a 16-bit i/o cycle will occur in three bclks. when nows y is asserted by an 8-bit device the default 6 bclks cycle is shortened to 4 or 5 bclks. nows y is an input when the esc performing bus translation cycles. nows y is an output when the esc internal registers are accessed. if chrdy and nows y are both asserted during the same clock then nows y will be ignored and wait-states will be added as a function of chrdy (chrdy has precedence over nows y ). osc in oscillator: osc is the 14.31818 mhz signal with 50% duty cycle. osc is used by the esc timers. rstdrv out reset drive: rstdrv is asserted by the esc. an asserted rstdrv causes a hardware reset of the devices on the isa bus. rstdrv is asserted whenever the reset y input to the esc is asserted. refresh y t/s refresh: refresh y is used by the esc as an output to indicate when a refresh cycle is in progress. it should be used to enable the sa [ 15:0 ] address to the row address inputs of all banks of dynamic memory on the isa bus so that when mrdc y goes active, the entire expansion bus dynamic memory is refreshed. memory slaves must not drive any data onto the bus during refresh and should not add wait states since this will affect the entire system throughput. as an output, this signal is driven directly onto the isa bus. this signal is an output only when the esc dma refresh is a master on the bus responding to an internally generated request for refresh. upon reset this pin will tristate. note that address lines [ 15:8 ] are driven during refresh, but the value is meaningless and is not used to refresh isa bus memory. refresh y may asserted by an expansion bus adapter acting as a 16-bit isa bus master. aen y out address enable: aen y is driven high for bus master cycles. aen y is driven low for dma cycles. and refresh cycles. aen y is used to disable i/o devices from responding to dma and refresh cycles. system designs which do not used the slots specific aens (aen [ 4:1 ] /eaen [ 4:1 ] ) provided by the esc can use the aen y signal to generate their own slot specific aens. aen [ 4:1 ] / out slot specific address enable/encoded slot specific address enable: these pins have a slightly different function depending on the esc eaen [ 4:1 ] configuration (mode select register bit 1 and bit 0). slot specific address enable: if the esc is programmed to support 4 eisa slots, these signals function as slot specific address enables (aen [ 4:1 ] ). encoded slot specific address enable: if the esc has been programmed to support more than 4 eisa slots, then these signals behave as encoded address enables (eaen [ 4:1 ] ). a discrete decoder is required to generate slot specific aens. refer to section 5.8.1 aen generation for a detailed description of these signals. 23
82374eb/82374SB 2.4 dma signal description pin name type description dreq [ 7:5,3:0 ] in dma request: dreq signals are either used to request dma service from the esc or used to gain control of the isa bus by a isa bus master. the active level (high or low) is programmed in the command registers. when the command register bit 6 is programmed to 0, dreq are asserted high, otherwise the dreq are asserted low. all inactive to active edges of dreq are assumed to be asynchronous. the request must remain asserted until the appropriate dack is negated. at power-up and after reset, these lines should be low (negated). dack y [ 7:5,3:0 ] out dma acknowledge: dack y indicate that a request for dma service from the dma subsystem has been recognized or that an isa bus master has been granted the bus. the level of the dack lines when asserted may be programmed to be either high or low. this is accomplished by programming the dma command register. these lines should be used to decode the dma slave device with the iorc y or iowc y line to indicate selection. if used to signal acceptance of a bus master request, this signal indicates when it is legal to assert master16 y . if the dma controller has been programmed for a timing mode other than compatible mode, and another device has requested the bus, anda4 m s time has elapsed, dack y will be negated and the transfer stopped before the transfer is complete. in this case, the transfer will be restarted at the next arbitration period in which the channel wins the bus. upon reset these lines are negated. eop t/s end of process: eop pin acts in one of two modes, and it is directly connected to the tc line of the isa bus. in the first mode, eop-in, the pin is an input and can be used by a dma slave to stop a dma transfer. in the second mode, tc-out, it is used as a terminal count output by dma slaves. an active pulse is generated when the byte counter reaches its last value. eop-in mode: during dma, for all transfer types, the eop pin is sampled by the esc. if it is sampled asserted, the address bus is tristated and the transfer is terminated. tc-out mode: the eop output will be asserted after a new address has been output if the byte count expires with that transfer. the eop (tc) will stay asserted until aen y is negated unless aen is negated during an autoinitialization. eop (tc) will be negated before aen is negated during an autoinitialization. intout mode: in this mode the eop signal has the same behavior as the chaining interrupt or the scatter-gather interrupt to the host processor (irq13). if a scatter-gather or chaining buffer is expired, eop will go active on the falling edge of bclk. only the currently active channel's interrupt will be reflected on this pin. other channel's with active interrupts pending will not affect the eop pin. whenever all the dma channels are not in use, the eop pin is kept in output mode and negated. after reset, the eop pin is kept in output mode and negated. 24
82374eb/82374SB 2.5 eisa arbitration signals pin name type description mreq [ 3:0 ] y in master request: mreq [ 3:0 ] y are slot specific signals used by eisa bus masters to request bus access. mreq y once asserted, must remain asserted until the corresponding mack y is asserted. the mreq y is negated on the falling edge of bclk slightly before the end of a master transfer. the la [] ,be [] y , m/io y , and w/r y lines should be floated on or before the rising edge of bclk after mreq y is negated. the end of the last bus cycle is derived from cmd y in this case. the mreq y signals are asserted on the falling edge of bclk. mreq y is always sampled on the rising edge of bclk. mreq y is synchronous with respect to bclk. after asserting mreq y , the corresponding master must not assert mreq y until 1.5 bclks after cmd y is negated. mreq [ 7:4 ] y /in master request/pci interrupt request: these pins behave in one of two modes depending on the state of the mode select register bit 1 and bit 0. pirq [ 0:3 ] y master request: mreq y lines are slot specific signals used by eisa bus masters to request bus access. this signal behave in the same manner as mreq [ 3:0 ] y signals. pci interrupt request: pirq y are used to generate asynchronous interrupts to the cpu via the programmable interrupt controller (82c59) integrated in the esc. these signals are defined as level sensitive and are asserted low. the pirqx y can be shared with pc compatible interrupts irq3:irq7, irq9:irq15. the pirqx y route control register determines which pci interrupt is shared with which pc compatible interrupt. register pins bit [ 1:0 ] mreq7 y / mreq6 y / mreq5 y / mreq4 y / pirq0 y pirq1 y pirq2 y pirq3 y 00 pirq0 y pirq1 y pirq2 y pirq3 y 01 pirq0 y pirq1 y mreq5 y mreq4 y 10 pirq0 y mreq6 y mreq5 y mreq4 y 11 mreq7 y mreq6 y mreq5 y mreq4 y 25
82374eb/82374SB pin name type description mack [ 3:0 ] y / out master acknowledge:/encoded master acknowledge: these pins behave in one of two modes depending on the state of the mode select register bit emack [ 3:0 ] 1 and bit 0. if the esc is programmed to support 4 eisa slots, then these pins are used as mack y . if the esc is programmed to support more than 4 eisa slots, then these pins are used as emack y master acknowledge: the mack [ 3:0 ] y signals are asserted from the rising edge of bclk at which time the bus master may begin driving the la [] ,be [] y , m/io y , and w/r y lines on the next falling edge of bclk. mack y will stay asserted until the rising edge of bclk when mreq y is sampled negated. mack y is sampled by eisa bus masters on the falling edge of bclk. if another device has requested the bus, mack y will be negated before mreq y is negated. when mack y is negated, the granted device has a maximum of 8 m s to negate mreq y and begin a final bus cycle. the esc may negate the mack y signal a minimum of one bclk after asserting it if another device (or refresh) is requesting the bus. upon reset mack y is negated. encoded master acknowledge: emack y behaves like mack y . the difference is that a discrete decoder is required to generate mack y for the eisa bus masters. refer to section 5.8.2 mack generation for details. 2.6 timer unit signal pin name type description spkr out speaker drive: spkr is the output of timer 1, counter 2 and is ``anded'' with port 061h bit 1 to provide speaker data enable. this signal drives an external speaker driver device, which in turn drives the isa system speaker. spkr has a 24 ma drive capability. upon reset, its output state is low. slowh y out slow down cpu: slowh y is the output of timer 2, counter 2. this counter is used to slow down the main cpu of its execution via the cpu's hold pin by pulse width modulation. the first read of i/o register in the 048h-04bh range will enable slowh y signal to follow the output of the timer 2, counter 2. upon reset, slowh y is negated. hardware reset (strapping option) during hardware reset this signal is an input and the level on the pin at the end of the reset sequence determines where bios resides. a high level indicates that bios resides on the x-bus and a low level indicates that bios resides on the isa bus. the status is used by the esc, to control the x-bus transceivers during bios access. note: for the 82374eb, this pin has an internal weak pull-up of approximately 8 k x . for proper configuration of the bios location during reset, a weak external pull- down resistor (approx. 500 x ) must be connected to this pin. an external pull-down resistor is not needed for the 82374SB. 26
82374eb/82374SB 2.7 interrupt controller signals pin name type description irq [ 15:9 ] ,in interrupt request: irq these signals provide both system board components and eisa bus i/o devices with a mechanism for asynchronously interrupting the cpu. irq8 y , the assertion mode of each interrupt can be programmed to be edge or level irq [ 7:3,1 ] triggered. an asserted irq input must remain asserted until after the falling edge of inta y . if the input is negated before this time, a default irq7 will occur when the cpu acknowledges the interrupt. irq8 y requires an external pull-up resistor (8 k x 10 k x ). intr out cpu interrupt: intr is driven by the esc to signal the cpu that an interrupt request is pending and needs to be serviced. it is asynchronous with respect to bclk or pciclk and it is always an output. the interrupt controllers must be programmed following a reset to ensure that this pin takes on a known state. upon reset the state of this pin is undefined. nmi out non-maskable interrupt: nmi is used to force a non-maskable interrupt to the cpu. the cpu registers an nmi when it detects a rising edge on nmi. nmi will remain active until a read from the cpu to the nmi register at port 061h is detected by the esc. this signal is set to low upon reset. 2.8 apic bus signals pin name type description apicclk in apic bus clock: apicclk provides the timing reference for the apic bus. changes on apicd [ 1:0 ] y are synchronous to the rising edge of apicclk. apicd [ 1:0 ] od apic data: apicd1 and apicd0 are the apic data bus signals. interrupt messages are sent/received over this bus. apic arbitration uses apicd1. 2.9 system power management signals (82374SB only) pin name type description stpclk y out stop clock: stpclk y is asserted by the esc in response to one of many maskable hardware or software events. for 3.3v processors that are not 5v tolerant, stpclk y is driven to the cpu stpclk y pin through a 5v to 3.3v translator. when the cpu samples stpclk y asserted it responds by stopping its internal clock. after a hard reset, this signal is negated. smi y out system management interrupt: smi y is asserted by the esc in response to one of many maskable hardware or software events. for 3.3v processors that are not 5v tolerant, smi y is driven to the cpu smi y pin through a 5v to 3.3v translator the cpu recognizes the falling edge of smi y as the highest priority interrupt in the system. the cpu responds by entering smm (system management mode). smi y is negated during and following reset. after a hard reset, this signal is negated. 27
82374eb/82374SB pin name type description extsmi y in external system management interrupt: extsmi y is a falling edge triggered input to the esc indicating that an external device is requesting the system to enter smm mode. when enabled via the smi enable register, a falling edge on extsmi y results in the assertion of the smi y signal to the cpu. extsmi y is an asynchronous input to the esc. init/test in initialize/test: on the 82374SB, the function of this pin is selected by the value on the gpcs0 y pin at reset. if gpcs0 y is low, init is selected and if gpcs0 y is high, test is selected. on the 82374eb, this pin only functions as the test pin. init init is connected to the init pin on the cpu and indicates to the esc that a cpu soft reset is occuring. when asserted, the esc ensures that stpclk y is negated when the cpu comes out of the soft reset. the esc also blocks smi y generation when init is asserted. test for test signal description, see the test signal section. stpgnt y in stpclk y grant: when asserted, stpgnt y indicates to the esc that a stop grant pci special cycle was recognized by the pceb. the esc may then negate the stpclk y signal when the stpclk y timer expires. 2.10 esc/pceb interface signals 2.10.1 arbitration and interrupt acknowledge control pin name type description eisahold out eisa hold: eisahold is used to request control of the eisa bus from its default owner, the pceb. this signal is synchronous to pciclk and is asserted when reset y is asserted. eisahlda in eisa hold acknowledge: eisahlda in used by the pceb to inform the esc that it has been granted ownership of eisa bus. this signal is synchronous to pciclk. pereq y /in pci to eisa request or interrupt acknowledge: pereq y /inta y is a dual function signal. the context of the signal pin is determined by the state of inta y eisahlda signal. when eisahlda is deasserted this signal has the context of interrupt acknowledge i.e. if pereq y /inta y is asserted it indicates to the esc that current cycle on the eisa is an interrupt acknowledge. when eisahlda is asserted this signal has the context of pci-to-eisa request i.e. if pereq y /inta y is asserted it indicates to the esc that pceb needs to obtain the ownership of the eisa bus on behalf of an pci agent. this signal is synchronous to the pciclk and it is driven inactive when reset y is asserted. 28
82374eb/82374SB 2.10.2 pceb buffer coherency control pin name type description nmflush y t/s new master flush: nmflush y is a bi-directional signal which is used to provide handshake between pceb and esc to control flushing of system buffers on behalf of eisa masters. during an eisa bus ownership change, before esc can grant the bus to the eisa master (or dma) it must ensure that system buffers are flushed and buffers pointing (potentially) towards eisa subsystem are disabled. the esc asserts nmflush y signal for one pci clock indicating the request for system buffer flushing. (after driving nmflush y asserted for 1 pci clock the esc tri-states nmflush y signal.) when pceb samples nmflush y asserted it starts immediately to drive nmflush y asserted and initiates internal and external requests for buffer flushing. after all buffers have been flushed (indicated by the proper handshake signals), the pceb negates nmflush y for 1 pci clock and stops driving it. when the esc samples the signal deasserted that indicates that all system buffers are flushed, it grants eisa bus to an eisa master (or dma). the esc resumes responsibility of default nmflush y driver and starts driving nmflush y deasserted until the next time a new eisa master (or dma) wins arbitration. this signal is synchronous with pciclk and is negated by the esc at reset. aflush y t/s apic flush: aflush y is bi-directional signal between the pceb and esc that controls system buffer flushing on behalf of the apic. after a reset the esc negates aflush y until the apic is initialized and the first interrupt request is recognized. sdcpyup out system (data) copy up: sdcpyup is used to control the direction of the byte copy operation. a high on the signal indicates a copy up operation where the lower byte lower word of the sd data bus is copied on to the higher byte or higher word of the bus. a low on the signal indicates a copy down operation where the higher byte(s) of the data bus are copied on to the lower byte(s) of the bus. the pceb uses the signal to perform the actual data byte copy operation during mis- matched cycles. sdoe [ 2:0 ] y out system data output enables: sdoe y enable the sd data output of the pceb data swap buffers on to eisa bus. the esc activates these signals only during mis-matched cycles. the pceb uses these signal to enable the sd data buffers as follows: sdoe0 y : enables byte lane 0 sd [ 7:0 ] sdoe1 y : enables byte lane 1 sd [ 15:8 ] sdoe2 y : enables byte lane 2 sd [ 23:16 ] and byte lane 3 sd [ 31:24 ] sdle [ 3:0 ] y out system data latch enables: sdle [ 3:0 ] y enable the latching of eisa data bus these signals are activated only during mis-matched cycles except pceb initiated write cycle. the pceb uses these signals to latch the sd data bus as follows: sdle0 y : latch byte lane 0 sd [ 7:0 ] sdle1 y : latch byte lane 0 sd [ 15:8 ] sdle2 y : latch byte lane 0 sd [ 23:16 ] sdle3 y : latch byte lane 0 sd [ 31:24 ] 29
82374eb/82374SB 2.11 integrated logic signals 2.11.1 eisa address buffer control pin name type description sale y out sa latch enable: sale y is directly connected to f543s which buffer the la addresses from the sa addresses. the rising edge of sale y latches the la address bit la [ 19:2 ] to the sa address bit sa [ 19:2 ] . lasaoe y out la to sa address output enable: lasaoe y is directly connected to the sa output buffer enables of the f543s. the esc asserts lasaoe y during eisa master cycles. when lasaoe y is asserted, the la to sa output buffers of the f543s are enabled. salaoe y out sa to la address output enable: salaoe y is connected to the la output buffer enables of the f543s. this signal functionally is the exact opposite of lasaoe y signals. the esc asserts salaoe y during isa master cycles. when lasaoe y is asserted, the sa to la output buffers of the f543s are enabled. 2.11.2 coprocessor interface pin name type description ferr y in numeric co-processor error: ferr y signal is tied to the co-processor error signal of the cpu. if ferr y is asserted (co-processor error detected by the cpu), an internal irq13 is be generated and the intr from the esc will be asserted. ignne y out ignore numeric error: ignne y is tied to the ignore numeric error pin of the cpu. ignne y is asserted and internal irq13 is negated from the falling edge of iowc y during an i/o write to location 00f0h. ignne y will remain asserted until ferr y is negated. during reset, this signal is driven low. 2.11.3 bios interface pin name type description lbioscs y out latched bios chip-select: lbioscs y indicates the that the current address is for the system bios. the esc generates this signal by decoding the eisa la addresses. the esc uses a transparent latch to latch the decoded signal. the lbioscs y is latched on the falling edge of bale and qualified with refresh y . 30
82374eb/82374SB 2.11.4 keyboard controller interface pin name type description kybdcs y out keyboard chip select: kybdcs y is connected to the chip select of the 82c42. kybdcs y is active for i/o addresses 0060h and 0064h. altrst y out alternate reset: altrst y is used to reset the cpu under program control. this signal is and'ed together externally with the reset signal (rstar y ) from the keyboard controller to provide a software means of resetting the cpu. this provides a faster means of reset than is provided by the keyboard controller. writin ga1tobit0in the port 92 register will cause this signal to pulse active (low) for approximately 4 bclk's. before another altrst y pulse can be generated, bit 0 must be written back to a 0. during reset, this signal is driven low. alta20 out alternate a20: alta20 is used to force a20m y to the cpu low for support of real mode compatible software. this signal is externally or'ed with the alta20 signal from the keyboard controller and cpurst to control the a20m y input of the cpu. writing a ``0'' to bit 1 of port 92h register will force alta20 inactive (low ). this in turn will drive a20m y to the cpu low, if a20gate from the keyboard controller is also low. writing a ``1'' to bit 1 of the port 92h register will force alta20 active (high), which in turn will drive a20m y to the cpu high, regardless of the state of alta20 from the keyboard controller. upon reset, this signal is driven low. abfull in auxiliary buffer full: abfull is tied directly to the abfull signal on the keyboard controller on the system board. this signal indicates that the keyboard controller auxiliary buffer for the mouse interface is full. see the clkdiv register desciption for programming the abfull function. if this function is not used, abfull should be tied low through a 1k resistor. 2.11.5 real time clock interface pin name type description rtcale out real time clock address latch enable: rtcale is directly connected to the system real time clock. the rtc uses this signal to latch the appropriate memory address. a write to port 070h with the appropriate real time clock memory address that will be written to or read from will cause rtcale to go active. rtcrd y / out real time clock read command/pci interrupt request 3: this signal pin has two functions and the function is selected via the mode select register. when pirq3 y functioning as rtcrd y , this signal is asserted for i/o reads from address 0071h. if the power on password protection is enabled (i/o port 92h bit 3 e 1), then for accesses to rtc addresses 36h 3fh (port 70h), rtcrd y will not be asserted. for details on pirq3 y , see the mode select register description. for the pirq3 y function, an external pull-up resistor (10-20 k) must be added to this signal. 31
82374eb/82374SB pin name type description rtcwr y / out real time clock write command/pci interrupt request 2: this signal pin has two functions, and the function is selected via the mode select register. pirq2 y when functioning as rtcwr y , this signal is asserted for i/o writes to address 0071h. if the power on password protection is enabled (i/o port 92h bit 3 e 1) then for accesses to rtc addresses 36h 3fh (port 70h) rtcwr y will not be generated. for details on pirq2 y , see the mode select register description. for the pirq2 y function, an external pull-up resistor (10k 20k) must be added to this signal. 2.11.6 floppy disk controller interface pin name type description fdccs y / out floppy disk controller chip select/pci interrupt request 1: this signal has two functions and the function is selected via the mode select register. as pirq1 y fdccs y is asserted for i/o cycles to the floppy drive controller. when functioning as fdccs y , this signal is also asserted when idecs1 y is decoded. see the mode select register description for details on the pirq1 y function of this signal. note that for the pirq1 y function, an external pull-up resistor (10 k x 20 k x ) must be added to this signal. dskchg in disk change: dskchg signal is tied directly to the dskchg signal of the floppy controller. this signal is inverted and driven onto system data line 7 (sd7) during i/o read cycles to floppy address locations 3f7h (primary) or 377h (secondary) as indicated by the table below. note that the primary and secondary locations are programmed in the x-bus address decode enable/disable register ``a''. fdccs y idecsx y state of sd7 state of decode decode (output) xbusoe y enabled enabled tri-stated enabled enabled disabled driven disabled via dskchg disabled enabled tri-stated disabled (note) disabled disabled tri-stated disabled note: this mode is not supported because of potential contention between the x-bus buffer and a floppy on the isa bus driving the system bus at the same time during shared i/o accesses. this signal is also used to determine if the floppy controller is present on the x-bus. it is sampled on the trailing edge of reset, and if high, the floppy is present. for systems that do not support a floppy via the esc, this pin should strapped low. if sampled low, the sd7 function, and xbusoe y will not be enable for accesses to the floppy disk controller. 32
82374eb/82374SB pin name type description dlight y / out fixed disk activity light/pci interrupt request 0: this signal has two functions, depending on the programming of the mode select register. as dlight y , pirq0 y this signal controls the fixed disk x light. when low, the light is on. when high, the light is off. if either bit 6 or bit 7 of the port 92 register is set t o a 1 (bit 6 and 7 are internally nor'ed together), dlight y is driven active (low). setting both bits 6 and 7 low will cause dlight y to be driven high. for the pirq0 y function, see the mode select register description. note that for the pirq0 y function, an external pull-up resistor (10 k x 20 k x ) must be added to this signal. 2.11.7 configuration ram interface pin name type description cramrd y out configuration ram read command: cramrd y is connected directly to the system configuration ram. the esc asserts cramrd y for i/o reads from the address range programmed into the low and high bytes of the configuration ram command registers. cramwr y out configuration ram write command: this is an active low output. cramwr y is connected directly to the system configuration ram. the esc activates cramwr y for i/o writes to the address range programmed into the low and high bytes of the configuration ram command registers. 2.11.8 x-bus control and general purpose decode pin name type description xbust/r y out x-bus data transmit/receive: xbust/r y is tied directly to the direction control of a 74f245 that buffers the x-bus data, xd(7:0), from the system data bus, sd(7:0). xbust/r y is driven high (transmit) during i/o and memory reads for eisa and isa masters. for dma cycles (channel 2 only), xbust/r y is driven high for the following cases: 1. memory read, i/o write cycles where lbioscs y is asserted. 2. i/o read, memory write cycles where digital output register bit 3 is set to 1. xbust/r y is driven low (receive) under all other conditions. 33
82374eb/82374SB pin name type description xbusoe y out x-bus data output enable: xbusoe y is tied directly to the output enable of a 74f245 that buffers the x-bus data, xd(7:0), from the system data bus, sd(7:0). for eisa and isa master memory read or write cycles, xbusoe y is asserted when lbioscs y is asserted. otherwise, xbusoe y is not asserted. for eisa and isa master i/o read or write cycles, sbusoe y is asserted if an isc supported x-bus device has been decoded, and the decoding for that device has been enabled via the proper configuration registers. an exception to this is during an i/o read access to floppy location 3f7h (primary) or 377h (secondary) if the ide decode space is disabled (i.e., ide is not present on the x-bus). in this case, xbusoe y is not asserted. xbusoe y is also not asserted during an i/o access to the floppy controller if dskchg is sampled low at reset. xbusoe y is not asserted during dma cycles, except for channel 2 dma. for channel 2 dma, xbusoe y is asserted. gpcs [ 2:0 ] y / out general purpose chip select/encoded chip select: these are dual function signals. the function of these pins is selected through the mode select ecs [ 2:0 ] register bit 4. general purpose chip select: gpcs [ 2:0 ] y are chip selects for peripheral devices. the peripheral devices can be mapped in the i/o range by programming the general purpose chip select base address registers and general purpose mask registers (offset 64h-6eh). encoded chip select: ecs [ 2:0 ] provide encoded chip select decoding for serial ports, parallel port, ide and general purpose devices. the device chip selects for the peripheral devices are generated by using a f138 with ecs [ 2:0 ] as inputs. hardware reset (test mode) 82374SB: during reset, gpcs0/ecs0 is an input signal. the level of this signal is sampled at the end of the reset sequence to determine whether the test pin is used as the current test function (sampled ``1'') or as the init signal (sampled ``0''). after reset, the existing gpcs/ecs functionality on this pin is maintained. note that an internal pull-up of approximately 8 k x is included on this pin. if the init mode on the test pin is to be selected, an external pull-down of approximately 500 x should be connected to the pin. 34
82374eb/82374SB 2.12 test signal pin name type description init/test in test: on the 82374eb, this pin only functions as a test pin. on the 82374SB, the function of this pin is selected by the value on the gpcs0 y pin at reset. if gpcs0 y is low, init is selected and if gpcs0 y is high, test is selected. init for init signal description, see the power management signal section. test test is used to tri-state all of the outputs. for normal operations, this signal should be tied to v cc . for test mode, this pin should be tied to ground. 3.0 register description the esc contains esc configuration registers, dma registers, timer unit registers, interrupt unit registers, and eisa configuration registers. all of the registers are accessible from the eisa bus. during a reset the esc sets its internal registers to predetermined default states. the default values are indicated in the individual register descriptions. the following notation is used to describe register access attributes: ro read only . if a register is read only, writes have no effect. wo write only . if a register is write only, reads have no effect. r/w read/write . a register with this attribute can be read and written. note that individual bits in some read/write registers may be read only. 3.1 configuration registers the esc's configuration registers are accessed through an indexing scheme. the index address register is located at i/o address 0022h, and the index data register is located at i/o address 0023h. the offset (data) written into the index address register selects the desired configuration register. data for the selected configu- ration register can be read from or written to by performing a read or a write to the index data register. see the address decode section for a summary of configuration register index addresses. some of the esc registers described in this section contain reserved bits. these bits are labeled ``r''. soft- ware must deal correctly with fields that are reserved. on reads, software must use appropriate masks to extract the defined bits and not rely on reserved bits being any particular value. on writes, software must ensure that the values of reserved bit positions are preserved. that is, the values of reserved bit positions must first be read, merged with the new values for other bit positions and then written back. in addition to reserved bits within a register, the esc's configuration space contains address locations that are marked ``reserved'' (see address decode section). the esc responds to accesses to these address loca- tions by completing the host cycle. when a reserved register location is read, 0000h is returned. writes to reserved registers have no effect on the esc. 35
82374eb/82374SB 3.1.1 escideesc id register address offset: 02h default value: 00h attribute: read/write size: 8 bits since the esc configuration registers are accessed by the index addressing mechanism using i/o ports 22h, and 23h, it is possible that another device in the system might use the same approach for configuration. in order to avoid contention with similar index register devices, the id register must be written with 0fh. the esc will not respond to accesses to any other configuration register until the id byte has been written in the esc id register. bit description 7:0 esc id byte: these bits must be written to a value of 0fh before the esc will respond to any other configuration register access. after a reset has occurred all of the configuration registers, except this register, are disabled. 3.1.2 riderevision id register address offset: 08h default value: 02h (82374eb: a-2 stepping) 03h (82374SB: b-0 stepping) attribute: read only size: 8 bits this 8-bit register contains device stepping information. writes to this register have no effect. bit description 7:0 revision id byte: these bits contain the stepping information about the device. the register is hardwired to the default value during manufacturing. the register is read only. writes have no effect on the register value. 3.1.3 msemode select register address offset: 40h default value: 20h attribute: read/write size: 8 bits this register selects the various functional modes of the esc. bit description 7 reserved 6 mreq [ 7:4 ] y /pirq [ 3:0 ] y enable: this bit enables the selected (mreq [ 7:4 ] y /pirq [ 3:0 ] y functionality. 1 e enabled; 0 e disabled 5 configuration ram address: this bit is used to enable or disable the configuration ram page address (cpg [ 4:0 ] ) generation. if this bit is set to 1, accesses to the configuration ram space will generate the ram page address on the la [ 31:27 ] y pins. if this bit is set to 0, the cpg [ 4:0 ] signals will not be activated. the default for this bit is 1. 36
82374eb/82374SB pin name description 4 general purpose chip selects: this bit is used to select the functionality of the gpcs [ 2:0 ] y / ecs [ 2:0 ] pins. if the bit is set to 0, the gpcs [ 2:0 ] y functionality is selected. if the bit is set to 1, the esc [ 2:0 ] functionality is selected. 3 system error: this bit is used to disable (0) or enable (1) the generation of nmi based on serr y signal pulsing active. when this bit e 1 (and nmis are enabled via the nmiertc register) and serr y is asserted, the nmi signal is asserted. when this bit e 0, the nmi signal is negated and serr y is disabled from generating an nmi. note that other nmi sources are enabled/disabled via the nmisc register. 2:0 pirqx mux/mapping control: these bits select muxing/mapping of pirq [ 3:0 ] y with mreq [ 7:4 ] and group of x-bus signals (dlight y , rtcwr y , rtcrd y ). different bit combinations select the number of eisa slots or group of x-bus signals which can be supported with the certain number of pirqx y signals by determining the functionality of pins aen [ 4:1 ] /eaen [ 4:1 ] , mack [ 3:0 ] y /emack [ 3:0 ] y , mreq [ 7:4 ] y /pirq [ 3:0 ] y , dlight y / pirq0 y , fdccs y /pirq1 y , rtcwr y /pirq2 y , rtcrd y /pirq3 y as shown in table 1. table 1. mode select register [ 2:0 ] bits signal function aen [ 4:1 ] / mack [ 3:0 ] y / mreq [ 7:4 y / dlight y / fddcs y / rtcwr y / rtcrd y / eaen [ 4:1 ] y emack [ 3:0 ] y pirq [ 0:3 ] y pirq0 y pirq1 y pirq2 y pirq3 y 000 eaen [ 4:1 ] y emack [ 3:0 ] y mreq [ 7:4 y pirq0 y pirq1 y pirq2 y pirq3 y 001 eaen [ 4:1 ] y emack [ 3:0 ] y mreq [ 7:4 y pirq0 y pirq1 y rtcwr y rtcrd y 010 eaen [ 4:1 ] y emack [ 3:0 ] y mreq [ 7:4 y pirq0 y fddcs y rtcwr y rtcrd y 011 eaen [ 4:1 ] y emack [ 3:0 ] y mreq [ 7:4 y dlight y fddcs y rtcwr y rtcrd y 100 aen [ 4:1 ] mack [ 3:0 ] y pirq [ 0:3 ] y dlight y fddcs y rtcwr y rtcrd y 101 eaen [ 4:1 ] y emack [ 3:0 ] y pirq0 y , dlight y fddcs y rtcwr y rtcrd y pirq1 y , mreq5 y , mreq4 y 110 eaen [ 4:1 ] y emack [ 3:0 ] y pirq0 y , dlight y fddcs y rtcwr y rtcrd y mreq6 y , mreq5 y , mreq4 y 111 eaen [ 4:1 ] y emack [ 3:0 ] y mreq [ 7:4 y dlight y fddcs y rtcwr y rtcrd y 37
82374eb/82374SB 3.1.4 bioscsaebios chip select a register address offset: 42h default value: 10h attribute: read/write size: 8 bits the lbioscs y signal is used to decode access to the motherboard bios. the esc decodes memory access to the following address ranges, and if the range has been enabled the lbioscs y signal is always asserted for memory reads in the enabled bios range. if the bios write enable bit is set in the configuration register bioscsb, the lbioscs y is also asserted for memory write cycles. bit description 7:6 reserved 5 enlarged bios: during memory access to locations fff80000h fffdffffh with this bit set, lbioscs y will be asserted for memory read cycles. if bit 3 of bioscsb is set, then lbioscs y will be asserted for write cycles as well. 4 high bios: during memory access to locations 0f0000h 0fffffh, ff0000h ffffffh, ffff0000h ffffffffh with this bit set, lbioscs y will be asserted for memory read cycles. if bit 3 of bioscsb is set, then lbioscs y will be asserted for write cycles as well. 3 low bios 4: during memory access to locations 0ec000h 0effffh, ffeec000h ffeeffffh, fffec000h fffeffffh with this bit set, lbioscs y will be asserted for memory read cycles. if bit 3 of bioscsb is set, then lbioscs y will be asserted for write cycles as well. 2 low bios 3: during memory access to locations 0e8000h 0ebfffh, ffee8000h ffeebfffh, fffe8000h fffebfffh with this bit set, lbioscs y will be asserted for memory read cycles. if bit 3 of bioscsb is set, then lbioscs y will be asserted for write cycles as well. 1 low bios 2: during memory access to locations 0e4000h 0e7fffh, ffee4000h ffee7fffh, fffe4000h fffe7fffh with this bit set, lbioscs y will be asserted for memory read cycles. if bit 3 of bioscsb is set, then lbioscs y will be asserted for write cycles as well. 0 low bios 1: during memory access to locations 0e0000h 0e3fffh, ffee0000h ffee3fffh, fffe0000h fffe3fffh with this bit set, lbioscs y will be asserted for memory read cycles. if bit 3 of bioscsb is set, then lbioscs y will be asserted for write cycles as well. 38
82374eb/82374SB 3.1.5 bioscsbebios chip select b register address offset: 43h default value: 00h attribute: read/write size: 8 bits the lbioscs y signal is used to decode access to the motherboard bios. the esc decodes memory access to the following address ranges, and if the range has been enabled the lbioscs y signal is always asserted for memory reads in the enabled bios range. if the bios write enable bit is set in the configuration register bioscsb, the lbioscs y is also asserted for memory write cycles. bit description 7:4 reserved 3 bios write enable: when enabled lbioscs y is asserted for memory read and write cycles for addresses in the decoded and enabled bios range, otherwise lbioscs y is asserted for memory read cycles only. 2 16 meg bios: during memory access to locations ff0000h ffffffh with this bit set, lbioscs y will be asserted for memory read cycles. if bit 3 of bioscsb is set, then lbioscs y will be asserted for write cycles as well. 1 high vga bios: during memory access to locations 0c4000h 0c7fffh with this bit set, lbioscs y will be asserted for memory read cycles. if bit 3 of bioscsb is set, then lbioscs y will be asserted for write cycles as well. 0 low vga bios: during memory access to locations 0c0000h 0c3fffh with this bit set, lbioscs y will be asserted for memory read cycles. if bit 3 of bioscsb is set, then lbioscs y will be asserted for write cycles as well. 39
82374eb/82374SB 3.1.6 clkdiveeisa clock divisor register address offset: 4dh default value: xx001000b attribute: read/write size: 8 bits this register is used to select the integer value used to divide the pci clock (pciclk) to generate the eisa bus clock (bclk) and enable/disable the co-processor error support. in addition, for the 82374SB, the register controls the abfull and kbfull functions. bit description 7:6 reserved 5 co-processor error: the state of this bit determines if the ferr y signal is connected to the esc internal irq13 interrupt signal. if this bit is set to 1, the esc will assert irq13 to the interrupt controller if ferr y signal is asserted. if this bit is set to 0, then the ferr y signal is ignored by the esc (i.e. this signal is not connected to any logic in the esc). 4 82374eb: reserved 82374SB: abfull (with irq12): when bit 4 e 0, the internal irq12 is directed to the interrupt controller and transitions on abfull have no affect on this interrupt signal. when bit 4 e 1, the assertion of abfull is latched and directed to the internal irq12 signal in the following manner: # if the interrupt controller is programmed for edge detect mode on irq12, a low-to-high transition is generated on the internal irq12 signal. transitions on the irq12 input pin are not reflected on the internal irq12 signal. # if the interrupt controller is programmed for level-sensitive mode, a high-to-low transition is generated on the internal irq12 signal. transitions on the irq12 input pin are also reflected on the internal irq12 signal. the latching of the abfull signal is cleared by an i/o read of address 60h (no aliasing) or by a hard reset. 3 82374eb: reserved 82374SB: keyboard full (kbfull): this bit selects the edge-detect kbfull function on the irq1 input signal. when bit 3 e 0, irq1 is directed to the interrupt controller. when bit 3 e 1 (default), irq1 is latched and directed to the interrupt controller. the latched irq1 is cleared by an i/o read of address 60h (no aliasing) or by a hard reset. 2:0 clock divisor: these bits are used to select the integer that is used to divide the pciclk down to generate the bclk. upon reset, these bits are set to 000b (divisor of 4). bit [ 2:0 ] divisor bclk 000 4 (33.33 mhz) 8.33 mhz 001 3 (25 mhz) 8.33 mhz 010 reserved 011 reserved 1xx reserved 40
82374eb/82374SB 3.1.7 pcsaeperipheral chip select a register address offset: 4eh default value: x0000111b attribute: read/write size: 8 bits this register is used to enable or disable accesses to the rtc, keyboard controller, floppy disk controller, and ide. disabling any of these bits will prevent the chip select and x-bus transceiver control signal (xbusoe y ) for that device from being generated. this register is also used to select which address range (primary or secondary) will be decoded for the resident floppy controller and ide. it also allows control of where the keyboard controller is physically located (x-bus or elsewhere).this insures that there is no contention with the x-bus transceiver driving the system data bus during read accesses to these devices. bit description 7 reserved 6 keyboard controller mapping: 0 e keyboard controller mapped to the x-bus (default). 1 e keyboard controller not mapped to the x-bus. when bit 6 e 0, the keyboard controller encoded chip select signal and the x-bus transceiver enable (xbusoe y ) are generated for accesses to address locations 60h (82374eb/sb), 62h (82374eb only), 64h (82374eb/sb) and 66h (82374eb only). when bit 6 e 1, the keyboard controller chip select signals are generated for accesses to these address locations. however xbusoe y is disabled. bit 1 must be 1 for either value of this configuration bit to decode an access to locations 60h, 62h, 64h, or 66h. 5,3:2 floppy disk and ide, floppy disk decodes: bits 2 and 3 are used to enable or disable the floppy locations as indicated. bit 2 defaults to enabled (1) and bit 3 defaults to disabled (0) when a reset occurs. bit 5 is used to select between the primary and secondary address range used by the floppy controller and the ide. only primary or only secondary can be programmed at any one time. this bit defaults to primary (0). the following table shows how these bits are used to select the floppy controller: address bit 2 bit 3 bit 5 dskchg fdccs y x xxx0 1 3f0h,3f1h x 1 0 1 0 3f2h 3f7h 1 x 0 1 0 (note) 370h,371h x 1 1 1 0 372h 37fh 1 x 1 1 0 (note) note: if ide decode is enabled, all accesses to locations 03f6h and 03f7h (primary) or 0376h and 0377h (secondary) will result in decode for idecs1 y (fdccs y will not be generated). an external and gate can be used to tie idecs1 y and fdccs y together to insure that the floppy is enabled for these accesses. 41
82374eb/82374SB pin name description 4 ide decode: bit 4 is used to enable or disable ide locations 1f0h 1f7h (primary) or 170h 177h (secondary) and 3f6h,3f7h (primary) or 376h,377h (secondary). 82374eb: when this bit is set to 0, the ide encoded chip select signals and the x-bus transceiver signal (xbusoe y ) are not generated for these addresses. 82374SB: when this bit is set to 0, the ide encoded chip select signals and the x-bus transceiver signal (xbusoe y ) are not generated for addresses 1f0h 1f7h (primary) or 170h 177h (secondary) and 3f6h, or 376h. note that read/write accesses to addresses 377h and 3f7h are not disabled and still generate xbusoe y . 1 keyboard controller decode: enables (1) or disables (0) the keyboard controller address locations 60h (82374eb/sb), 62h (82374eb only), 64h (82374eb/sb), and 66h (82374eb only). when this bit is set to 0, the keyboard controller encoded chip select signals and the x-bus transceiver signal (xbusoe y ) are not generated for these locations. note that the value of this bit affects control function (keyboard controlling mapping) provided by bit 6 of this register. 0 bit 0: real time clock decode: enables (1) or disables (0) the rtc address locations 70h 77h. when this bit is set to 0, the rtc encoded chip select signals rtcale, rtcrd, rtcwr y , and xbusoe y signals are not generated for these addresses. 3.1.8 pcsbeperipheral chip select b register address offset: 4fh default value: cfh attribute: read/write size: 8 bits this register is used to enable or disable generation of the x-bus transceiver signal (xbusoe y ) for accesses to the serial ports and parallel port locations. when disabled, the xbusoe y signal for that device will not be generated. bit description 7 cram decode: this bit is used to enable (1) or disable (0) i/o write accesses to location 0c00h and i/o read/write accesses to locations 0800h 08ffh. the configuration ram read and write (cramrd y , cramwr y ) strobes are valid for accesses to 0800h 08ffh. 6 port 92 decode: this bit is used to disable (0) access to port 92. this bit defaults to enable (1) at pcirst. 5:4 parallel port decode: these bits are used to select which parallel port address range (lpt1, 2,or 3) is decoded. bits [ 5:4 ] decode 00 lpt1 (3bch 3bfh) 01 lpt2 (378h 37fh) 10 lpt3 (278h 27fh) 11 disabled 42
82374eb/82374SB pin name description 3:2 serial port b address decode: if either com1 or com2 address ranges are selected, these bits default to disabled upon pcirst. bits [ 3:2 ] decode 00 3f8h 3ffh (com1) 01 2f8h 2ffh (com2) 10 reserved 11 port a disabled 1:0 serial port a address decode: if either com1 or com2 address ranges are selected, these bits default to disabled upon pcirst. bits [ 1:0 ] decode 00 3f8h 3ffh (com1) 01 2f8h 2ffh (com2) 10 reserved 11 port a disabled 3.1.9 eisaid [ 4:1 ] eeisa id registers address offset: 50h, 51h, 52h, 53h default value: 00h, 00h, 00h, 00h attribute: read/write size: 8 bits each these 8 bit registers contain the eisa motherboard id. the data in the register is reflected on the data bus for i/o cycles addressed to 0c80h 0c83h respectively. bit description 7:0 eisa id byte: these bits contain the eisa motherboard id information. on power up these bits default to 00h. these bit are written with the id value during configuration. the value of these bits are reflected in i/o registers 0c80h 0c83h. 3.1.10 sgrbaescatter/gather relocate base address register address offset: 57h default value: 04h attribute: read/write size: 8 bits the value programmed in this register determines the high order i/o address of the s-g registers. the default value is 04h. bit description 7:0 s-g relocate byte: these bits determine the i/o location of the scatter gather registers. the scatter-gather register relocation range is xx10h xx3fh (default 0410h 043fh). these bits determine the byte 1 of the i/o address. address signals la [ 15:8 ] are compared against the contents of this register (bit [ 7:0 ] ) to determine i/o accesses to the scatter-gather registers. the default on power up is 04h. 43
82374eb/82374SB 3.1.11 apicbaseeapic base address relocation address offset: 59h default value: 00h attribute: read/write size: 8 bits the apicbase register provides the modifier for the apic base address. 82374eb: apic is mapped in the cpu memory space at the locations fec0 e x000h and fec0 e x010h (x e 0-fh). the value of ``x'' is defined by bits [ 5:2 ] . thus, the relocation register provide s a 4 kbyte address granularity. the default value of 00h provides apic unit mapping at the addresses fec00000h and fec00010h. 82374SB: apic is mapped in the cpu memory space at the locations fec0 e xy00h and fec0 e xy10h (x e 0-fh, y e 0,4,8,ch). the value of ``y'' is defined by bits [ 1:0 ] and value of ``x'' is defined by bits [ 5:2 ] . thus, the relocation register provides a 1 kbyte address granularity (i.e. potentially up to 64 i/o apics can be uniformly addresses in the memory space). the default value of 00h provides apic unit mapping at the addresses fec00000h and fec00010h. bit description 7:6 reserved 5:2 x-base addresser/w: bits [ 5:2 ] are compared to host address bits a [ 15:12 ] , respectively. 1:0 82374eb: reserved 82374SB: y-base addresser/w: bits [ 1:0 ] are compared to host address bits a [ 11:10 ] , respectively. 3.1.12 pirq [ 0:3 ] y epirq route control registers address offset: 60h, 61h, 62h, 63h default value: 80h attribute: read/write size: 8 bits these registers control the routing of pci interrupts (pirq [ 0:3 ] y ) to the pc compatible interrupts. each pci interrupt can be independently routed to 1 of 11 compatible interrupts. interrupt steering programming considerations when using the pci programmable interrupt steering feature, the following programming considerations apply: 1. any interrupt steered to by a pirqx y must be programmed to level sensitive mode. 2. for an interrupt used as a pirqx y , that irq pin is also level sensitive. it is not permissible to use an interrupt on the eisa/isa bus as edge triggered as well as on the pci bus as level sensitive. 3. registers that must be programmed when using a pirqx y include the mode select registers, edge level registers, pirq [ 3:0 ] y route control registers, and the interrupt mask registers (listed in suggested programming order) 44
82374eb/82374SB bit description 7 routing of interrupts: when enabled (0) this bit routes the pci interrupt signal to the pc compatible interrupt signal specified in bits [ 6:0 ] . after a reset or a power-on this bit is disabled (set to 1). 6:0 irqx y routing bits: these bits specify which irq signal to generate when the pci interrupt for this register has been triggered. bits [ 6:0 ] irqx y bits [ 6:0 ] irqx y 0000000 reserved 0001001 irq9 0000001 reserved 0001010 irq10 0000010 reserved 0001011 irq11 0000011 irq3 0001100 irq12 0000100 irq4 0001101 reserved 0000101 irq5 0001110 irq14 0000110 irq6 0001111 irq15 0000111 irq7 0010000 to 0001000 reserved 1111111 reserved 3.1.13 gpcsla [ 2:0 ] egeneral purpose chip select low address register address offset: 64h, 68h, 6ch default value: 00h attribute: read/write size: 8 bits this register contains the low byte of the general purpose peripheral mapping address. the contents of this register are compared with the la [ 7:0 ] address lines. the contents of this register, the gpcsha register and the gpcsm register control the generation the gpcs [ 2:0 ] y signal or the esc [ 2:0 ] signal (101, 110 combina- tion). if mode select register (offset 40h) bit 4 e 1, offset register 6ch is ignored. bit description 7:0 gpcs low address byte: the contents of these bits are compared with the address lines la [ 7:0 ] to generate the gpcs [ 2:0 ] y signal or the ecs [ 2:0 ] combination for this register. the mask register (gpcsm [ 2:0 ] ) determines which bits to use during the comparison. 3.1.14 gpcsha [ 2:0 ] egeneral purpose chip select high address register address offset: 65h, 69h, 6dh default value: c0h attribute: read/write size: 8 bits this register contains the high byte of the general purpose peripheral mapping address. the contents of this register are compared with the la [ 15:8 ] address lines. the contents of this register, the gpcsla register and the gpcsm register control the generation the gpcs [ 2:0 ] y signal or the esc [ 2:0 ] signal (101, 110 combina- tion). if mode select register (offset 40h) bit 4 e 1, offset register 6dh is ignored. bit description 7:0 gpcs high address byte: the contents of these bits are compared with the address lines la [ 15:8 ] to generate the gpcs [ 2:0 ] y signal or the ecs [ 2:0 ] combination for this register. 45
82374eb/82374SB 3.1.15 gpcsm [ 2:0 ] egeneral purpose chip select mask register address offset: 66h, 6ah, 6eh default value: 00h attribute: read/write size: 8 bits this register contains the mask bits for determining the address range for which the gpcsx y signals are generated. if a register bit is set t o a 1 then the corresponding bit in the gpcsl register is not compared with the address signal in the generation of the gpcsx y signals. if mode select register (offset 40h) bit 4 e 1, offset register 6eh is ignored. bit description 7:0 gpcs mask register: the contents of these bits are used to determine which bits to compare gpcsla [ 2:0 ] with the address lines la [ 7:0 ] . a 1 bit means the bit should not be compared. 3.1.16 gpxbcegeneral purpose peripheral x-bus control register address offset: 6fh default value: xxxx x000b attribute: read/write size: 8 bits the register controls the generation of the x-bus buffer output enable (xbusoe y ) signal for i/o accesses to the peripherals mapped in the general purpose chip select address decode range. this register determines if the general purpose peripheral is placed on the xbus or not. if the general purpose peripheral is on the x-bus, then the corresponding bit is set to 1. otherwise the bit is set to 0. bit description 7:3 reserved 2 xbusoe y generation for gpcs2 y : when this bit is enabled xbusoe y will be generated when gpcs2 y is generated; 1 e enabled, 0 e disabled. 1 xbusoe y generation for gpcs1 y : when this bit is enabled xbusoe y will be generated when gpcs1 y is generated; 1 e enabled, 0 e disabled. 0 xbusoe y generation for gpcs0 y : when this bit is enabled xbusoe y will be generated when gpcs0 y is generated;1 e enabled, 0 e disabled. 46
82374eb/82374SB 3.1.17 pacepci/apic control register address offset: 70h default value: 00h attribute: read/write size: 8 bits the pac register controls the operation of the intr signal in apic/pic configuration and the routing of the system management interrupt (smi). bit description 7:2 reserved 1 smi routing control (smirc): when smirc e 1, the smi is routed via the apic. when smirc e 0, the smi is routed via the smi y signal. note that when smrc e 1, intr can not be routed through the apic, since it is sharing the apic interrupt input with smi y . 0 intr routing control (intrc): when apic is enabled (in mixed or pure apic mode), this bit allows the esc's external intr signal to be masked (forces intr to the inactive state but does not tri-states the signal). thus, the cpu's intr pin can be used (by providing a simple -gate) for the apic local interrupt (lintrx). however, intr must not be masked via this bit when apic is disabled and intr is the only mechanism to signal the 8259 recognized interrupts to the cpu. when intrc e 1, intr is disabled (apic must be enabled). when intrc e 0, intr is enabled. 3.1.18 testcetest control register address offset: 88h default value: 00h attribute: read/write size: 8 bits this register provides control for esc manufacturing test modes. the functionality of this register is reserved. 3.1.19 smicntlesmi control register address offset: a0h default value: 08h attribute: read/write size: 8 bits for the 82374SB, the smicntl register provides fast off timer control, stpclk y enable/disable, and cpu clock scaling. this register also enables/disables the system management interrupt (smi). bit description 7 reserved: must be 0 when writing this register. 6:4 reserved 3 fast off timer freeze (ctmrfrz): this field enables/disables the fast off timer. when this bit is 1, the fast off timer stops counting. this prevents time-outs from occurring while executing smm code. when this bit is 0, the fast off timer counts. 47
82374eb/82374SB pin name description 2 stpclk y scaling enable (cstpclksc): this bit enables/disables control of the stpclk y high/low times by the clock scaling timers. when bit 2 e 1, the stpclk y signal scaling control is enabled. when enabled (and bit 1 e 1, enabling the stpclk y signal), the high and low times for the stpclk y signal are controlled by the clock scaling stpclk y high timer and clock scaling stpclk y low timer registers, respectively. when bit 2 e 0 (default), the scaling control of the stpclk y signal is disabled. 1 stpclk y signal enable (cstpclke): this bit permits software to place the cpu into a low power state. when bit 1 e 1, the stpclk y signal is enabled and a read from the apmc register causes stpclk y to be asserted. when bit 1 e 0 (default), the stpclk y signal is disabled and is negated (high). software can set this bit to 0 by writin ga0toitorbyany write to the apmc register. 0 smi y gate (csmigate): when bit 0 e 1, the smi y signal is enabled and a system management interrupt condition causes the smi y signal to be asserted. when bit 0 e 0 (default), the smi y signal is masked and negated. this bit only affects the smi y signal and does not effect the detection/recording of smi events (i.e., this bit does not effect the smi status bits in the smireq register). thus, smi conditions can be pending when this bit is set to 1. if an smi is pending when this bit is set to 1, the smi y signal is asserted. 3.1.20 smienesmi enable register address offset: a2-a3h default value: 0000h attribute: read/write size: 16 bits for the 82374SB, his register enables the generation of smi (asserting the smi y signal) for the associated hardware events (bits [ 5:0 ] ), and software events (bit 7). when a hardware event is enabled, the occurrence of a corresponding event results in the assertion of smi y , if enabled via the smicntl register. the smi y is asserted independent of the current power state (power-on or fast off). the default for all sources in this register is disabled. bit description 15:8 reserved 7 apmc write smi enable: this bit enables smi for writes to the apmc register. when bit 7 e 1, writes to the apmc register generate an smi. when bit 7 e 0, writes to the apmc register do not generate an smi. 6 extsmi y smi enable: when bit 6 e 1, asserting the extsmi y input signal generates an smi. when bit 6 e 0, asserting extsmi y does not generate an smi. 5 fast off timer smi enable: this bit enables the fast off timer to generate an smi. when bit 5 e 1, the timer generates an smi when it decrements to zero. when bit 5 e 0, the timer does not generate an smi. 4 irq12 smi enable (ps/2 mouse interrupt): this bit enables the irq12 signal to generate an smi. when bit 4 e 1, asserting the irq12 input signal generates an smi. when bit 4 e 0, asserting irq12 does not generate an smi. 3 irq8 smi enable (rtc alarm interrupt): this bit enables the irq8 signal to generate an smi. when bit 3 e 1, asserting the irq8 input signal generates an smi. when bit 3 e 0, asserting irq8 does not generate an smi. 48
82374eb/82374SB bit description 2 irq4 smi enable (com2/com4 interrupt or mouse): thsi bit enables the irq4 signal to generate an smi. when bit 1 e 1, asserting the irq3 input signal generates an smi. when bit 2 e 0, asserting irq4 does not generate an smi. 1 irq3 smi enable (com1/com3 interrupt or mouse): this bit enables the irq3 signal to generate an smi. when bit 1 e 1, asserting the irq3 input signal generates an smi. when bit 1 e 0, asserting irq3 does not generate an smi. 0 irq1 smi enable (keyboard interrupt): this bit enables the irq1 signal to generate an smi. when bit 0 e 1, asserting the irq1 input signal generates an smi. when bit 0 e 0, asserting irq1 does not generate an smi. 3.1.21 seeesystem event enable register address offset: a4-a7h default value: 00000000h attribute: read/write size: 32 bits for the 82374SB, this register enables hardware events as system events or break events for power manage- ment control. note that all of the functional bits in the see register provide system event control. in addition, all bits also provide break event control. the default for each system/break event in this register is disabled. system events: activity by these events can keep the system from powering down. when a system event is enabled, the corresponding hardware event activity prevents a fast off powerdown condition. anytime the corresponding hardware event occurs (signal is asserted), the fast off timer is re-loaded with its initial count. break events: these events can awaken a powered down system. when a break event is enabled, the corresponding hardware event activity powers up the system by negating stpclk y . note that stpclk y is not negated until the stop grant special cycle has been generated by the cpu. thus, from the time that stpclk y is asserted until the stop grant cycle is returned, the occurrence of subsequent break events are latched in the esc. note: init is always enabled as a break event. however, init only causes a break event after a stop grant special cycle has been received. if init is asserted while stpclk y is active and then negated be- fore the stop grant cycle is received, init does not cause a break event. bit description 31 fast off smi enable (fsmien): when bit 31 e 1 (enabled), an smi causes a system event that re- loads the fast off timer and a break event that negates the stpclk y signal. when bit 31 e 0 (disabled), an smi does not re-load the fast off timer or negate the stpclk y signal. 30 reserved 29 fast off nmi enable (fnmien): when bit 29 e 1 (enabled), an nmi (e.g., parity error) causes a system event that re-loads the fast off timer and a break event that negates the stpclk y signal. when bit 29 e 0 (disabled), an smi does not re-load the fast off timer or negate the stpclk y signal. 49
82374eb/82374SB bit description 28:16 reserved 15:3 fast off irq [ 15:3 ] enable (firq [ 15:3 ] en): these bits are used to prevent the system from entering fast off and break any current powerdown state when the selected hardware interrupt occurs. when a bit e 1 (enabled), the corresponding interrupt causes a system event that re-loads the fast off timer and a break event that negates the stpclk y signal. when a bit e 0 (disabled), the corresponding interrupt does not re-load the fast off timer or negate the stpclk y signal. 2 reserved 1:0 fast off irq [ 1:0 ] enable (firq [ 1:0 ] en): these bits are used to prevent the system from entering fast off and break any current powerdown state when the selected hardware interrupt occurs. when a bit e 1, the corresponding interrupt causes a system event that re-loads the fast off timer and a break event that negates the stpclk y signal. when a bit e 0 (disabled), the corresponding interrupt does not re-load the fast off timer or negate the stpclk y signal. 3.1.22 ftmrefast off timer register address offset: a8h default value: 0fh attribute: read/write size: 8 bits for the 82374SB, the fast off timer is used to indicate (through an smi) that the system has been idle for a pre-programmed period of time. the fast off timer consists of a count-down timer and the value programmed into this register is loaded into the fast off timer when an enabled system event occurs. when the timer expires, an smi special cycle is generated. when the fast off timer is enabled (bit 3 e 0 in the smicntl register), the timer counts down from the value loaded into this register. the count time interval is one minute. when the fast off timer reaches 00h, an smi is generated and the timer is re-load with the value programmed into this register. if an enabled system event occurs before the fast off timer reaches 00h, the fast off timer is re-loaded with the value in this register. note: before writing to the ftmr register, the fast off timer must be stopped via bit 3 of the smicntl register. in addition, this register should not be programmed to 00h. bit description 7:0 fast off timer value: bits [ 7:0 ] contain the starting count value. a read from the ftmr register returns the value last written. 3.1.23 smireqesmi request register address offset: aa-abh default value: 00h attribute: read/write size: 16 bits for the 82374SB, the smireq register contains status bits indicating the cause of an smi. when an enabled event causes an smi, the esc automatically sets the corresponding event's status bit to 1. software sets the status bits to 0 by writin ga0to them. only the esc hardware can set status bits to a 1. software 50
82374eb/82374SB writing a 1 to any of the status bits has no effect. if software attempts to set a status bit to 0 at the same time that the esc is setting it to 1, the bit is set to 1 (i.e., the esc hardware dominates). the smi handler can query the status bits to see what caused the smi and then branch to the appropriate routine. as the individual routines complete the handler resets the appropriate status bit by writing a 0 to the corresponding bit. each of the smireq bits is set by the esc in response to the activation of the corresponding smi event. if the smi event is still active when the corresponding smireq bit is set to 0, the esc does not set the status bit back t o a 1 (i.e., there is only one status indication per active smi event). when an irqx signal is asserted, the corresponding rirqx bit is set to a 1. if the irqx signal is still active when software sets the rirqx bit to 0, rirqx is not set back to a 1. the irqx may be negated before software sets the rirqx bit to 0. if the rirqx bit is set to 0 at the same time a new irqx is activated, rirqx remains at 1. this indicates to the smi handler that a new smi event has been detected. note: 1. the smireq bits are set, cleared, or read independently of each other and independently of the csmigate bit in the smicntl register. 2. if an irqx is set in level mode and shared by two devices, the irq should not be enabled as an smi y event. the esc's smireq bits are essentially set with an edge. when the second irq occurs on a shared irq, there is no second edge and the smi y will not be generated for the second irq. bit description 15:8 reserved 7 apm smi status (rapmc): the esc sets this bit to 1 to indicate that a write to the apm control register caused an smi. software sets this bit t oa0by writin ga0toit. 6 extsmi y smi status (rext): the esc sets this bit to 1 to indicate that extsmi y caused an smi. software sets this bit t oa0by writin ga0toit. 5 fast off timer expired status (rfot): the esc sets this bit to 1 to indicate that the fast off timer expired and caused an smi. software sets this bit t oa0by writin ga0toit. when the fast off timer expires, the esc sets this bit to a 1. note that the timer re-starts counting one the next clock after it expires. 4 irq12 request smi status (rirq12): the esc sets this bit to 1 to indicate that irq12 caused an smi. software sets this bit t oa0by writin ga0toit. 3 irq8 y request smi status: the esc sets this bit to 1 to indicate that irq8 y caused an smi. software sets this bit t oa0by writin ga0toit. 2 irq4 request smi status: the esc sets this bit to 1 to indicate that irq4 caused an smi. software sets this bit t oa0by writin ga0toit. 1 irq3 request smi status: the esc sets this bit to 1 to indicate that irq3 caused an smi. software sets this bit t oa0by writin ga0toit. 0 irq1 request smi status: the esc sets this bit to 1 to indicate that irq1 caused an smi. software sets this bit t oa0by writin ga0toit. 51
82374eb/82374SB 3.1.24 ctltmrclock scale stpclk y low timer address offset: ach default value: 00h attribute: read/write size: 8 bits for the 82374SB, the value in this register defines the duration of the stpclk y asserted period when bit 2 in the smicntl register is set to 1. the value in this register is loaded into the stpclk y timer when stpclk y is asserted. however, the timer does not start until the stop grant bus cycle is received. the stpclk y timer counts using a 32 m s clock. bit description 7:0 clock scaling stpclk y low timer value: bits [ 7:0 ] define the duration of the stpclk y asserted period during clock throttling. 3.1.25 ctltmrheclock scale stpclk y high timer address offset: aeh default value: 00h attribute: read/write size: 8 bits for the 82374SB, the value in this register defines the duration of the stpclk y negated period when bit 2 in the smicntl register is set to 1. the value in this register is loaded into the stpclk y timer when stpclk y is negated. the stpclk y timer counts using a 32 m s clock. bit description 7:0 clock scaling stpclk y high timer value: bits [ 7:0 ] define the duration of the stpclk y negated period during clock throttling. 3.2 dma register description the esc contains dma circuitry that incorporates the functionality of two 82c37 dma controllers (dma1 and dma2). the dma registers control the operation of the dma controllers and are all accessible from the eisa bus. this section describes the dma registers. unless otherwise stated, a reset sets each register to its default value. the operation of the dma is further described in chapter 6.0, dma controller. 3.2.1 dcomecommand register register location: 08hechannels 0-3 0d0hechannels 4-7 default value: 00h attribute: write only size: 8 bits this 8-bit register controls the configuration of the dma. it is programmed by the microprocessor in the program condition and is cleared by reset or a master clear instruction. note that disabling channels 4-7 will also disable channels 0-3, since channels 0-3 are cascaded onto channel 4. the dreq and dack y channel assertion sensitivity is assigned by channel group, not per individual channel. for priority resolution the dma 52
82374eb/82374SB consists of two logical channel groups channels 0-3 (controller 1-dma1) and channels 4-7 (controller 2- dma2). both groups may be assigned fixed priority, one group can be assigned fixed priority and the second rotating priority, or both groups may be assigned rotating priority. a detailed description of the channel priority scheme is found in the dma functional description, section 6.5. following a reset or dma master clear, both dma-1 and dma-2 are enabled in fixed priority, the dreq sense level is active high, and the dack y assertion level is active low. bit description 7 dack y assert level: bit 7 controls the dma channel request acknowledge (dack y ) assertion level. following reset, the dack y assertion level is active low. the low level indicates recognition and acknowledgment of the dma request to the dma slave requesting service. writin ga0tobit7 assigns active low as the assertion level. whe na1is written to this bit, a high level on the dack y line indicates acknowledgment of the request for dma service to the dma slave. 6 dreq sense assert level: bit 6 controls the dma channel request (dreq) assertion detect level. following reset, the dreq sense assert level is active high. in this condition, an active high level sampled on dreq is decoded as an active dma channel request. writin ga0tobit6 assigns active high as the sense assert level. whe na1is written to this bit, a low level on the dreq line is decoded as an active dma channel request. 5 reserved: must be 0. 4 dma group arbitration: each channel group is individually assigned either fixed or rotating arbitration priority. at reset, each group is initialized in fixed priority. writin ga0tobit4 assigns fixed priority to the channel group, while writin g a 1 assigns rotating priority to the group. 3 reserved: must be 0. 2 dma group enable: writin ga1to this bit disables the dma channel group, while writin ga0to this bit enables the dma channel group. both channel groups are enabled following reset. disabling channel group 4-7 also disables channel group 0-3, which is cascaded through channel 4. 1:0 reserved: must be 0. 53
82374eb/82374SB 3.2.2 dcmedma channel mode register register location: 0bhechannels 0-3 0d6hechannels 4-7 default value: 000000xxb attribute: write only size: 8 bits each channel has a mode register associated with it. the mode registers provide control over dma transfer type, transfer mode, address increment/decrement, and autoinitialization. when writing to the register, bits [ 1:0 ] determine which channel's mode register will be written and are not stored. only bits [ 7:2 ] are stored in the mode register. this register is set to the default value upon reset and master clear. its default value is verify transfer, autoinitialize disable, address increment, and demand mode. channel 4 defaults to cascade mode and cannot be programmed for any mode other than cascade mode. bit description 7:6 dma transfer mode: each dma channel can be programmed in one of four different modes: single transfer, block transfer, demand transfer and cascade. bits [ 7:6 ] transfer mode 00 demand mode 01 single mode 10 block mode 11 cascade mode 5 address increment/decrement select: bit 5 controls address increment/decrement during multi- byte dma transfers. when bit 5 e 0, address increment is selected. when bit 5 e 1, address decrement is selected. address increment is the default after a pcirst y cycle or master clear command. 4 autoinitialize enable: when bit 4 e 1, the dma restores the base page, address, and word count information to their respective current registers following a terminal count (tc). when bit 4 e 0, the autoinitialize feature is disabled and the dma does not restore the above mentioned registers. a pcirst y or master clear disables autoinitialization (sets bit 4 to 0). 3:2 dma transfer type: verify, write and read transfer types are available. verify transfer is the default transfer type upon pcirst y or master clear. write transfers move data from an i/o device to memory. read transfers move data from memory to an i/o device. verify transfers are pseudo transfers; addresses are generated as in a normal read or write transfer and the device responds to eop etc. however, with verify transfers, the isa memory and i/o cycle lines are not driven. bit combination 11 is illegal. when the channel is programmed for cascade ( [ 7:6 ] e 11) the transfer type bits are irrelevant. bits [ 3:2 ] transfer type 00 verify transfer 01 write transfer 10 read transfer 11 illegal 1:0 dma channel select: bits [ 1:0 ] select the dma channel mode register that will be written by bits [ 7:2 ] . bits [ 1:0 ] channel 00 channel 0 (4) 01 channel 1 (5) 10 channel 2 (6) 11 channel 3 (7) 54
82374eb/82374SB 3.2.3 dcemedma channel extended mode register register location: 040bhechannels 0-3 04d6hechannels 4-7 default value: 000000xxb attribute: write only size: 8 bits each channel has an extended mode register. the register is used to program the dma device data size, timing mode, eop input/output selection, and stop register selection. when writing to the register, bits [ 1:0 ] determine which channel's extended mode register will be written and are not stored. only bits [ 7:2 ] are stored in the extended mode register. four timing modes are available: isa-compatible, a, b, and burst. the default bit values for each dma group are selected upon reset. a master clear or any other programming sequence will not set the default register settings. the default programmed values for dma1 channels 0-3 are 8-bit i/o count by bytes, compatible timing, and eop output. the default values for dma2 channels 4-7 are 16-bit i/o count by words with shifted address, compatible timing, and eop output. these default settings provide a rigorous isa-compatible dma implementation. note: dma1/dma2 refer to the original pc-at implementation which used two discrete 8237 dma control- lers. in this context, dma1 refers to dma channels 0-3 and dma2 refers to dma channels 4-7. the pc-at used channel 4 (channel 0 of dma2) as a cascade channel for dma1. consequently, chan- nel 4 is not used in compatible dma controllers although the compatible dma registers are kept to maintain compatibility with the original pc-at. because channel 4 is not used, the dma controller does not support extended registers for channel 4. bit description 7 stop register: bit 7 of this register selects whether or not the stop registers associated with this channel are to be used. normally the stop registers will not be used. this function was added to help support data communication or other devices that work from a ring buffer in memory. upon reset, the bit 7 is set to 0-stop register disabled. the detailed stop register functional description discusses the use of the stop registers. 6 eop input/output: bit 6 of the extended mode register selects whether the eop signal is to be used as an output during dma on this channel or an input. eop will generally be used as an output, as was available on the pcat. the input function was added to support data communication and other devices that would like to trigger an autoinitialize when a collision or some other event occurs. the direction of eop is switched when dack is changed (when a different channel wins the arbitration and is granted the bus). there may be some overlap of the esc driving the eop signal along with the dma slave. however, during this overlap both devices will be driving the signal to a low level (negated). for example, assume channel 2 is about to go inactive (dack negated) and channel 1 is about to go active. if channel 2 is programmed for ``eop out'' and channel 1 is programmed for ``eop in'', when channel 2's dack is negated and channel 1's dack is asserted, the esc may be driving eop to a low value on behalf of channel 2 at the same time the device connected to channel 1 is driving eop in to the esc, also at an inactive level. this overlap will only last until the esc eop output buffer is tristated, and will not effect the dma operation. upon reset, the value of bit 6 is 0 (eop output selected). 55
82374eb/82374SB bit description 5:4 dma cycle timing mode: the esc supports four dma transfer timings: isa-compatible, type a, type b, and burst. each timing and its corresponding code are described below. upon reset, compatible timing is selected and the value of these bits is ``00''. the cycle timings noted below are for a bclk (8.33 mhz maximum bclk frequency). dma cycles to isa expansion bus memory will default to compatible timing if the channel is programmed in one of the performance timing modes (type a, b, or burst). 00 compatible timing dma slaves on the isa bus may run compatible dma cycles. bits [ 5:4 ] must be programmed to 00. compatible timing is provided for dma slave devices, which, due to some design limitation, cannot support one of the faster timings. compatible timing runs at 9 bclks (1080 ns/single cycle) and 8 bclks (960 ns/cycle) during the repeated portion of a block or demand mode transfers. 01 type ``a'' timing type ``a'' timing is provided to allow shorter cycles to eisa memory. if isa memory is decoded, the system automatically reverts to isa dma type compatible timing on a cycle-by-cycle basis. type ``a'' timing runs at 7 bclks (840 ns/single cycle) and 6 bclks (720 ns/cycle) during the repeated portion of a block or demand mode transfer. type ``a'' timing varies from compatible timing primarily in shortening the memory operation to the minimum allowed by system memory. the i/o portion of the cycle (data setup on write, i/o read access time) is the same as with compatible cycles. the actual active command time is shorter, but it is expected that the dma devices which provide the data access time or write data setup time should not require excess ior y or iow y command active time. because of this, most isa dma devices should be able to use type ``a'' timing. 10 type ``b'' timing type ``b'' timing is provided for 8-/16- bit isa or eisa dma devices which can accept faster i/o timing. type ``b'' only works with eisa memory. type ``b'' timing runs at 6 bclks (720 ns/single cycle) and 4 bclks (480 ns/cycle) during the repeated portion of a block or demand mode transfer. type ``b'' timing requires faster dma slave devices than compatible timing in that the cycles are shortened so that the data setup time on i/o write cycles is shortened and the i/o read access time is required to be faster. some of the current isa devices should be able to support type ``b'' timing, but these will probably be more recent designs using relatively fast technology. 11 type ``c'' timing (burst) burst timing is provided for high performance eisa dma devices. the dma slave device needs to monitor the exrdy and iorc y or iowc y signals to determine when to change the data (on writes) or sample the data (on reads). this timing will allow up to 33 mbytes per second transfer rate with a 32-bit dma device and 32-bit memory. note that 8- or 16-bit dma devices are supported (through the programmable address size) and that they use the ``byte lanes'' natural to their size for the data transfer. as with all bursts, the system will revert to two bclk cycles if the memory does not support burst. when a dma burst cycle accesses non-burst memory and the dma cycle crosses a page boundary into burstable memory, the esc will continue performing non-burst cycles. this will not cause a problem since the data is still transferred correctly. 56
82374eb/82374SB bit description 3:2 addressing mode: the esc supports 8-, 16-, and 32-bit dma device data sizes. the four data size options are programmable with bits [ 3:2 ] . both the 8 bit i/o, ``count by bytes'' mode and the 16-bit i/o, ``count by words'' (address shifted) mode are isa compatible. the 16-bit and 32-bit i/o, ``count by bytes'' modes are eisa extensions. byte assembly/disassembly is performed by the eisa bus controller. each of the data transfer size modes is discussed below. 00 8-bit i/o, ``count by bytes'' mode in 8 bit i/o, ``count by bytes'' mode, the address counter can be programmed to any address. the count register is programmed with the ``number of bytes minus 1'' to transfer. 01 16-bit i/o, ``count by words'' (address shifted) mode in ``count by words'' mode (address shifted), the address counter can be programmed to any even address, but must be programmed with the address value shifted right by one bit. the page registers are not shifted during dma transfers. thus, the least significant bit of the low page register is ignored when the address is driven out onto the bus. the word count register is programmed with the number of words minus 1 to be transferred. 10 32-bit i/o, ``count by bytes'' mode in 32-bit ``count by bytes'' mode, the address counter can be programmed to any byte address. for most dma devices, however, it should only be programmed to a dword aligned address. if the starting address is not dword aligned then the dma controller will do a partial dword transfer during the first and last during the first and last transfers if necessary. the bus controller logic will do the byte/word assembly necessary to read or write any size memory device and both the dma and bus controllers support burst for this mode. in this mode, the address register is usually incremented or decremented by four and the byte count is usually decremented by four. the count register should be programmed with the number of bytes to be transferred minus 1. 11 16-bit i/o, ``count by bytes'' mode in 16-bit ``count by bytes'' mode, the address counter can be programmed to any byte address. for most dma devices, however, it should be programmed only to even addresses. if the address is programmed to an odd address, then the dma controller will do a partial word transfer during the first and last transfer if necessary. the bus controller will do the byte/word assembly necessary to write any size memory device. in this mode, the address register is incremented or decremented by two and the byte count is decremented by the number of bytes transferred during each bus cycle. the word count register is programmed with the ``number of bytes minus 1'' to be transferred. this mode is offered as an extension of the two isa compatible modes discussed above. this mode should only be programmed for 16 bit isa dma slaves. 1:0 dma channel select: bits [ 1:0 ] select the particular channel that will have its dma channel extend mode register programmed with bits [ 7:2 ] . bits [ 1:0 ] channel 00 channel 0 (4) 01 channel 1 (5) 10 channel 2 (6) 11 channel 3 (7) 57
82374eb/82374SB 3.2.4 dredma request register register location: 09hechannels 0-3 0d2hechannels 4-7 default value: 000000xxb attribute: write only size: 8 bits each channel has a request bit associated with it in one of the two request registers. the request register is used by software to initiate a dma request. the dma responds to the software request as though dreq [ x ] is asserted. these requests are non-maskable and subject to prioritization by the priority encoder network (refer to the channel priority functional description). each register bit is set or reset separately under software control or is cleared upon generation of a tc. the entire register is cleared upon reset or a master clear. it is not cleared upon a rstdrv output. to set or reset a bit, the software loads the proper form of the data word. bits [ 1:0 ] determine which channel request register will be written. in order to make a software request, the channel must be in block mode. the request register status for dma1 and dma2 is output on bits [ 7:4 ] of a status register read to the appropriate port. bit description 7:3 reserved: must be 0. 2 dma channel service request: writin ga0tobit2 resets the individual software dma channel request bit. writin ga1tobit2 will set the request bit. the request bit for each dma channel is reset to 0 upon a reset or a master clear. 1:0 dma channel select: bits [ 1:0 ] select the dma channel mode register to program with bit 2. bits [ 1:0 ] channel 00 channel 0 01 channel 1 (5) 10 channel 2 (6) 11 channel 3 (7) 3.2.5 mask registerewrite single mask bit register location: 0ahechannels 0-3 0d4hechannels 4-7 default value: 000001xxb attribute: write only size: 1 bit/channel each dma channel has a mask bit that can disable an incoming dma channel service request dreq [ x ] assertion. two registers store the current mask status for dma1 and dma2. setting the mask bit disables the incoming dreq [ x ] for that channel. clearing the mask bit enables the incoming dreq [ x ] . a channel's mask bit is automatically set when the current word count register reaches terminal count (unless the channel is programmed for autoinitialization). each mask bit may also be set or cleared under software control. the entire register is also set by a reset or a master clear. setting the entire register disables all dma requests until a clear mask register instruction allows them to occur. this instruction format is similar to the format used with the request register. individually masking dma channel 4 (dma controller 2, channel 0) will automatically mask dma channels [ 3:0 ] , as this channel group is logically cascaded onto channel 4. setting this mask bit disables the incoming dreq's for channels [ 3:0 ] . 58
82374eb/82374SB bit description 7:3 reserved: must be 0. 2 dma channel mask set/clear: writin ga1tobit2 sets the mask bit and disables the incoming dreq for the selected channel. writin ga0tobit2 clears the mask bit and enables the incoming dreq for the elected channel. 1:0 dma channel select: bits [ 1:0 ] select the dma channel mode register to program with bit 2. bits [ 1:0 ] channel 00 channel 0 (4) 01 channel 1 (5) 10 channel 2 (6) 11 channel 3 (7) 3.2.6 wambewrite all mask bits register register location: 0fhechannels 0-3 0dehechannels 4-7 default value: 0fh attribute: read/write size: 8 bits this command allows enabling and disabling of incoming dreq assertions by writing the mask bits for each controller, dma1 or dma2, simultaneously rather than by individual channel as is done with the ``write single mask bit'' command. two registers store the current mask status for dma1 and dma2. setting the mask bit disables the incoming dreq [ x ] for that channel. clearing the mask bit enables the incoming dreq [ x ] . unlike the ``write single mask bit'' command, this command includes a status read to check the current mask status of the selected dma channel group. when read, the mask register current status appears on bits [ 3:0 ] .a channel's mask bit is automatically set when the current word count register reaches terminal count (unless the channel is programmed for autoinitialization). the entire register is also set by a reset or a master clear. setting the entire register disables all dma requests until a clear mask register instruction allows them to occur. two important points should be taken into consideration when programming the mask registers. first, individu- ally masking dma channel 4 (dma controller 2, channel 0) will automatically mask dma channels [ 3:0 ] ,as this channel group is logically cascaded onto channel 4. second, masking off dma controller 2 with a write to port 0deh will also mask off dreq assertions from dma controller 1 for the same reason: when dma channel 4 is masked, so are dma channels 0-3. 59
82374eb/82374SB bit description 7:4 reserved: must be 0. 3:0 channel mask bits: setting the bit(s) t o a 1 disables the corresponding dreq(s). setting the bit(s) to a 0 enables the corresponding dreq(s). bits [ 3:0 ] are set to 1 upon pcirst y or master clear. when read, bits [ 3:0 ] indicate the dma channel [ 3:0 ] ( [ 7:4 ] ) mask status. bit channel 0 0(4) 1 1(5) 2 2(6) 3 3(7) note: disabling channel 4 also disables channels 0-3 due to the cascade of dma1 through channel 4 of dma2. 3.2.7 dsedma status register register location: 08hechannels 0-3 0d0hechannels 4-7 default value: 00h attribute: read only size: 8 bits each dma controller has a read-only status register. a status register read is used when determining which channels have reached terminal count and which channels have a pending dma request. bits [ 3:0 ] are set every time a tc is reached by that channel. these bits are cleared upon reset and on each status read. bits [ 7:4 ] are set whenever their corresponding channel is requesting service. bit description 7:4 request status: when a valid dma request is pending for a channel (on its dreq signal line), the corresponding bit is set to 1. when a dma request is not pending for a particular channel, the corresponding bit is set to 0. the source of the dreq may be hardware, a timed-out block transfer, or a software request. note that channel 4 does not have dreq or dack lines, so the response for a read of dma2 status for channel 4 is irrelevant. bit channel 40 5 1(5) 6 2(6) 7 3(7) 3:0 terminal count status: when a channel reaches terminal count (tc), its status bit is set to 1. if tc has not been reached, the status bit is set to 0. note that channel 4 is programmed for cascade, and is not used for a dma transfer. therefore, the tc bit response for a status read on dma2 for channel 4 is irrelevant. bit channel 00 1 1(5) 2 2(6) 3 3(7) 60
82374eb/82374SB 3.2.8 db&caedma base and current address register (8237 compatible segment) register location: 000hedma channel 0 002hedma channel 1 004hedma channel 2 006hedma channel 3 0c0hedma channel 4 0c4hedma channel 5 0c8hedma channel 6 0cchedma channel 7 default value: 0000h attribute: read/write size: 16 bits per channel each channel has a 16-bit current address register. this register holds the value of the 16 least significant bits of the full 32-bit address used during dma transfers. the address is automatically incremented or decrement- ed after each transfer and the intermediate values of the address are stored in the current address register during the transfer. this register is written to or read from by the microprocessor or bus master in successive 8-bit bytes. the programmer must issue the ``clear byte pointer flip-flop'' command to reset the internal byte pointer and correctly align the write prior to programming the current address register. after clearing the byte pointer flip-flop, the first write to the current address port programs the low byte, bits [ 7:0 ] , and the second write programs the high byte, bits [ 15:8 ] . this procedure applies for read cycles also. it may also be re-initial- ized by an autoinitialize back to its original value. autoinitialize takes place only after a tc or eop. each channel has a base address register located at the same port address as the corresponding current address register. these registers store the original value of their associated current registers. during autoini- tialize these values are used to restore the current registers to their original values. the base registers are written simultaneously with their corresponding current register in successive 8-bit bytes by the microproces- sor. the base registers cannot be read by any external agents. in scatter-gather mode these registers store the lowest 16-bits of the current memory address. during a scatter-gather transfer the dma will load a reserve buffer into the base memory address register. in chaining mode these register store the lowest 16-bits of the current memory address. the cpu will program the base register set with a reserve buffer. bit description 15:0 base and current address: these bits represent the 16 least significant address bits used during dma transfers. together with the dma low page register, they help form the isa-compatible 24-bit dma address. as an extension of the isa compatible functionality, the dma high page register completes the 32-bit address needed when implementing esc extensions such as dma to the pci bus slaves that can take advantage of full 32-bit addressability. upon reset or master clear, the value of these bits is 0000h. 61
82374eb/82374SB 3.2.9 db&cbwedma base and current byte/word count register (8237 compatible segment) register location: 001hedma channel 0 003hedma channel 1 005hedma channel 2 007hedma channel 3 0c2hedma channel 4 0c6hedma channel 5 0cahedma channel 6 0cehedma channel 7 default value: 0000h attribute: read/write size: 16 bits per channel each channel has a 16-bit current byte/word count register. this register determines the lower 16 bits for the number of transfers to be performed. there is a total of 24 bits in the byte/word count registers. the uppermost 8 bits are in the high byte/word count register. the actual number of transfers will be one more than the number programmed in the current byte/word count register (i.e., programming a count of 100 will result in 101 transfers). the byte/word count is decremented after each transfer. the intermediate value of the byte/word count is stored in the register during the transfer. when the value in the register goes from zero to 0ffffffh, a tc will be generated. following the end of a dma service it may also be re-initialized by an autoinitialization back to its original value. autoinitialize can occur only when a tc occurs. if it is not autoinitialized, this register will have a count of ffffh after tc. when the extended mode register is programmed for ``count by word'' transfers to/from a 16-bit i/o, with shifted address, the byte/word count will indicate the number of 16-bit words to be transferred. when the extended mode register is programmed for ``count by byte'' transfers, the byte/word count will indicate the number of bytes to be transferred. the number of bytes does not need to be a multiple of the transfer size in this case. each channel has a base byte/word count register located at the same port address as the corresponding current byte/word count register. these registers store the original value of their associated current regis- ters. during autoinitialize these values are used to restore the current registers to their original values. the base registers cannot be read by any external agents. in scatter-gather mode these registers store the lowest 16-bits of the current byte/word count. during a scatter-gather transfer the dma will load a reserve buffer into the base byte/word count register. in chaining mode these register store the lowest 16-bits of the current byte/word count. the cpu will then program the base register set with a reserve buffer. bit description 15:0 base and current byte/word count: these bits represent the lower 16 byte/word count bits used when counting down a dma transfer. upon reset or master clear, the value of these bits is 0000h. 62
82374eb/82374SB 3.2.10 dma base and current high byte/word count register; dma base high byte/ word count register register location: 401hedma channel 0 403hedma channel 1 405hedma channel 2 407hedma channel 3 4c6hedma channel 5 4cahedma channel 6 4cehedma channel 7 default value: 00h attribute: read/write size: 8 bits per channel each channel has a 8-bit current high byte/word count register. this register provides the uppermost 8 bits for the number of transfers to be performed. the byte/word count is decremented after each transfer. the intermediate value of the byte/word count is stored in the register during the transfer. when the value in the register goes from zero to ffffh, a tc may be generated. following the end of a dma service it may also be re-initialized by an autoinitialization back to its original value. autoinitialize can occur only when a tc occurs. if it is not autoinitialized, this register will have a count of ffffh after tc. the high byte/word count register must be the last byte/word count register programmed. writing to the 8237 compatible byte/word count registers will clear the high byte/word count register to 00h. when the extended mode register is programmed for ``count by word'' transfers to/from a 16-bit i/o, with shifted address, the byte/word count will indicate the number of 16-bit words to be transferred. when the extended mode register is programmed for ``count by byte'' transfers, the byte/word count will indicate the number of bytes to be transferred. the number of bytes does not need to be a multiple of the transfer size in this case. each channel has a base high byte/word count register located at the same port address as the correspond- ing current high byte/word count register. these registers store the original value of their associated current registers. during autoinitialize these values are used to restore the current registers to their original values. normally, the base registers are written simultaneously with their corresponding current register in successive 8 bit bytes by the microprocessor. however, in chaining mode only the base register set is programmed and the current register is not effected. the base registers cannot be read by any external agents. in scatter-gather mode these registers store the lowest 8 bits of the current high byte/word count. during a scatter-gather transfer the dma will load a reserve buffer into the base high byte/word count register. in chaining mode these register store the lowest 8 bits of the current high byte/word count. the cpu will then program the base register set with a reserve buffer. bit description 7:0 base and current high byte/word count: these bits represent the 8 high order byte/word count bits used when counting down a dma transfer. upon reset or master clear, the value of these bits is 00h. 63
82374eb/82374SB 3.2.11 dma memory low page register; dma memory base low page register register location: 087hedma channel 0 083hedma channel 1 081hedma channel 2 082hedma channel 3 08bhedma channel 5 089hedma channel 6 08ahedma channel 7 default value: 00h attribute: read/write size: 8 bits per channel each channel has an 8-bit low page register associated with it. the dma memory low page register contains the eight second most-significant bits of the 32-bit address. it works in conjunction with the dma controller's high page register and current address register to define the complete (32-bit) address for the dma channel. this 8-bit register is read or written directly by the processor or bus master. it may also be re-initialized by an autoinitialize back to its original value. autoinitialize takes place only after a tc or eop. each channel has a base low page address register located at the same port address as the corresponding current low page register. these registers store the original value of their associated current low page registers. during autoinitialize these values are used to restore the current low page registers to their original values. the 8-bit base low page registers are written simultaneously with their corresponding current low page register by the microprocessor. the base low page registers cannot be read by any external agents. during scatter-gather these registers store the 8 bits from the third byte of the current memory address. during a scatter-gather transfer the dma will load a reserve buffer into the base memory address register. in chaining mode these register store the 8 bits from the third byte of the current memory address. the cpu will program the base register set with a reserve buffer. bit description 7:0 dma low page and base low page: these bits represent the eight second most-significant address bits when forming the full 32-bit address for a dma transfer. upon reset or master clear, the value of these bits is 00h. 3.2.12 dmapedma page register register location: 080h, 84h, 85h, 86h, 88h, 8ch, 8dh, 8eh default value: xxh attribute: read/write size: 8 bits these registers have no effect on the dma operation. these registers provide extra storage space in the i/o space for dma routines. bit description 7:0 dma page: these bit have no effect on the dma operation. these bits only provide storage space in the i/o map. 64
82374eb/82374SB 3.2.13 dmalpredma low page refresh register register location: 08fh default value: xxh attribute: read/write size: 8 bits the contents of this register are driven on the address byte 2 (la [ 23:16 ] y ) during refresh cycles. bit description 7:0 dma low page refresh: the contents of the bits are driven on to the address bus(la [ 23:16 ] ) during refresh. 3.2.14 dmamhpgedma memory high page register; dma memory base high page register register location: 0487hedma channel 0 0483hedma channel 1 0481hedma channel 2 0482hedma channel 3 048bhedma channel 5 0489hedma channel 6 048ahedma channel 7 default value: 00h attribute: read/write size: 8 bits per channel each channel has an 8-bit high page register. the dma memory high page register contains the eight most- significant bits of the 32-bit address. it works in conjunction with the dma controller's low page register and current address register to define the complete (32-bit) address for the dma channels and corresponds to the ``current address'' register for each channel. this 8-bit register is read or written directly by the processor or bus master. it may also be re-initialized by an autoinitialize back to its original value. autoinitialize takes place only after a tc or eop. this register is reset to 00h during the programming of both the low page register and the current address register. thus, if this register is not programmed after the other address and low page registers are pro- grammed, then its value will be zero. in this case, the dma channel will operate the same as an 82c37 (from an addressing standpoint). this is the address compatibility mode. if the high 8 bits of the address are programmed after the other addresses, then the channel will modify its operation to increment (or decrement) the entire 32-bit address. this is unlike the 82c37 ``page'' register in the original pcs which could only increment to a 64k boundary (for 8-bit channels) or 128k (for 16-bit chan- nels). this is extended address mode. in this mode, the isa bus controller will generate the signals memr y and memw y only for addresses below 16 mbytes. each channel has a base high page address register located at the same port address as the corresponding current high page address register. these registers store the original value of their associated current registers. during autoinitialize these values are used to restore the current registers to their original values. the 8 bit base high page registers are written simultaneously with their corresponding current register by the microprocessor. the base registers cannot be read by any external agents. during scatter-gather these registers store the 8 bits from the highest byte of the current memory address. during a scatter-gather transfer the dma will load a reserve buffer into the base memory address register. 65
82374eb/82374SB in chaining mode these register store the 8 bits from the highest byte of the current memory address. the cpu will program the base register set with a reserve buffer. bit description 7:0 dma high page and base high page: these bits represent the eight most-significant address bits when forming the full 32-bit address for a dma transfer. upon reset or master clear, the value of these bits is 00h. 3.2.15 dmahpgredma high page register refresh register location: 048fh default value: xxh attribute: read/write size: 8 bits per channel the contents of this register are driven on the address byte 3 (la [ 31:24 ] y ) during refresh cycles. bit description 7:0 dma high page refresh: the contents of the bits are driven on to the address bus (la [ 31:24 ] ) during refresh. 3.2.16 stop registers register location: 04e0hech0 stop reg bits [ 7:2 ] 04e1hech0 stop reg bits [ 15:8 ] 04e2hech0 stop reg bits [ 23:16 ] 04e4hech1 stop reg bits [ 7:2 ] 04e5hech1 stop reg bits [ 15:8 ] 04e6hech1 stop reg bits [ 23:16 ] 04e8hech2 stop reg bits [ 7:2 ] 04e9hech2 stop reg bits [ 15:8 ] 04eahech2 stop reg bits [ 23:16 ] 04echech3 stop reg bits [ 7:2 ] 04edhech3 stop reg bits [ 15:8 ] 04eehech3 stop reg bits [ 23:16 ] 04f4hech5 stop reg bits [ 7:2 ] 04f5hech5 stop reg bits [ 15:8 ] 04f6hech5 stop reg bits [ 23:16 ] 04f8hech6 stop reg bits [ 7:2 ] 04f9hech6 stop reg bits [ 15:8 ] 04fahech6 stop reg bits [ 23:16 ] 04fchech7 stop reg bits [ 7:2 ] 04fdhech7 stop reg bits [ 15:8 ] 04fehech7 stop reg bits [ 23:16 ] default value: see below attribute: read/write size: see below the stop registers are used to support a common data communication structure, the ring buffer. the ring buffer data structure and stop register operation are described in section 6.7.4. the stop registers, in con- junction with a channel's base and current address and byte count registers, are used to define a fixed portion of memory for use by the ring buffer data structure. following a reset, these registers are not reset to 0. 66
82374eb/82374SB bit description 23:2 upper, mid, lower stop bits: these 22 bits provide the stop address. if the stop function is enabled then the channel will stop whenever its memory address matches the stop address. bits [ 23:16 ] are the upper stop bits. bits [ 15:8 ] are the mid stop bits and bits [ 7:2 ] are the lower stop bits. bits [ 1:0 ] are not used and are don't cares. 3.2.17 chainechaining mode register register location: 040ahechannels 0-3 04d4hechannels 4-7 default value: 000000xxb attribute: write only size: 8 bits each channel has a chaining mode register. the chaining mode register enables or disables dma buffer chaining and indicates when the dma base registers are being programmed. when writing to the register, bits [ 1:0 ] determine which channel's chaining mode register to program. the chaining status and interrupt status for all channels can be determined by reading the chaining mode status, channel interrupt status, and chain buffer expiration control registers. the chaining mode register is reset to zero upon reset, access (read or write) of a channel's mode register or extended mode register, or a master clear. the values upon reset are disable chaining mode and generate irq13. bit description 7:5 reserved: must be 0. 4 buffer expired signal: after one of the two buffers in the dma expires then the dma will inform the cpu that the next buffer should be loaded into the base register set. this bit determines whether irq13 or eop should be used to inform the cpu that the buffer is complete; 1 e generate tc, 0 e generate irq13; 1 e programming complete, 0 e don't start chaining. 3 base register programming: after the reserve buffer's address and word count are written to the base register set, this bit should be set to 1 to inform the dma that the second buffer is ready for transfer. 2 buffer chaining mode: bit 2 enables the chaining mode logic. if the bit is set to 1 after the initial dma address and word count are programmed, then the base address and word count are available for programming the next buffer in the chain. 1 e enable chaining, 0 e disable chaining. 1:0 dma channel select: bits [ 1:0 ] select the dma channel mode register to program with bits [ 4:2 ] . bits [ 1:0 ] channel 00 0or4 01 1or5 10 2or6 11 3or7 67
82374eb/82374SB 3.2.18 chainstaechaining mode status register register location: 04d4h default value: 00h attribute: read only size: 8 bits this register is read only and is used to determine if chaining mode for a particular channel is enabled or disabled . a 1 read in this register indicates that the channel's chaining mode is enabled . a 0 indicates that the chaining mode is disabled. all chaining mode bits are disabled after a reset with reset. after the dma is used in chaining mode the cpu will need to clear the chaining mode enable bit if non-chaining mode is desired. bit description 7:5, chaining mode status: if this bit is set to 1 then this channel has chaining enabled by writing 1 to bit 2 of the chaining mode register. this bit can be reset to 0 by either writin ga0tobit2ofthe chaining 3:0 mode register or reset being asserted or by a master clear command. 4 reserved 3.2.19 chintstechannel interrupt status register register location: 040ah default value: 00h attribute: read only size: 8 bits channel interrupt status is a read only register and is used to indicate the source (channel) of a dma chaining interrupt on irq13. the dma controller asserts irq13 after reaching terminal count, with chaining mode enabled. it does not assert irq13 during the initial programming sequence that loads the base registers. after a reset, a read of this register will produce 00h. bit description 7:5, chaining interrupt status: when a channel interrupt status read returns a 0, bits [ 7:5,3:0 ] indicates that channel did not assert irq13. when a channel interrupt status read returns a 1, then that channel 3:0 asserted irq13 after reaching a terminal count. 4 reserved 3.2.20 chainbecechain buffer expiration control register register location: 040ch default value: 00h attribute: read only size: 8 bits this register is read only and reflects the outcome of the expiration of a chain buffer. a chain buffer expiration control register bit with 0 indicates the dma controller asserts irq13 when the dma controller reaches terminal count. a 1 indicates the dma controller asserts tc when the dma controller reaches terminal count. this bit is programmed in bit 4 of the chaining mode register. 68
82374eb/82374SB bit description 7:5, chaining buffer expired: when a chain buffer expiration control read returns 0, bit [ 7:5,3:0 ] indicates that channel [ 7:5,3:0 ] will assert irq13 when the dma channel reaches terminal count. when a 3:0 chain buffer expiration control read returns 1, bit [ 7:5,3:0 ] indicates that channel [ 7:5,3:0 ] will assert tc when the dma controller reaches terminal count. this bit will reset to 0 following a reset. 4 reserved 3.2.21 scatgaescatter-gather command register register location: 0410hechannels 0 0411hechannels 1 0412hechannels 2 0413hechannels 3 0415hechannels 5 0416hechannels 6 0417hechannels 7 default value: 00xxxx00b attribute: write only, relocateable size: 8 bits the scatter-gather command register controls operation of the descriptor table aspect of s-g transfers. the s-g command register is write only. the current s-g transfer status can be read in the s-g channel's corre- sponding s-g status register. the s-g command register can initiate a s-g transfer, and stop a transfer. scatter-gather commands are issued with command codes. bits [ 1:0 ] are used to implement the code mecha- nism. the s-g codes are described in the table below. bit 7 is used to control the irq13/eop assertion that follows a terminal count. bit 6 controls the effect of bit 7. common scatter-gather command writes are listed in table 2. table 2. scatter gather command bits command bits 7654 3210 no s-g operation (s-g noop) 0000 0000b start s-g xx00 0001b stop s-g xx00 0010b issue irq13 on terminal count 0100 00xxb issue eop on terminal count 1100 00xxb note that the ``x'' don't care states in table 2 do not preclude programming those bits during the command write. for instance, for any s-g command code on bits [ 1:0 ] , an optional selection of irq13 or eop can take place if bit 7 is set to 1 and the appropriate choice is made for bit 6. all 0's in the command byte indicate an s- g noop: no s-g command is issued, and eop/irq13 modification is disabled. note that an eop/irq13 modification can be made while disabling the s-g command bits (bits [ 1:0 ] e 00b); conversely, an s-g com- mand may be issued while eop/irq13 modification is disabled (bit 6 e 0b). after a reset, or master clear, irq13 is disabled and eop is enabled. 69
82374eb/82374SB the start command assumes the base and current registers are both empty and will request a prefetch automatically. it also sets the status register to s-g active, base empty, current empty, not terminated, and next null indicator to 0. the eop/irq13 bit will still reflect the last value programmed. bit description 7 eop/irq13 selection: bit 7 is used to select whether eop or irq will be asserted at termination caused by the last buffer expiring. the last buffer can be either the last buffer in the list or the last buffer loaded in the dma while it is suspended. if this bit is set to 1 then eop will be asserted whenever the last buffer is completed. if this bit is set to 0 then irq13 will be asserted whenever the last buffer is completed. eop can be used to alert an expansion bus i/o device that a scatter-gather termination condition was reached; the i/o device in turn can assert its own interrupt request line, and invoke a dedicated interrupt handling routine. irq13 should be used whenever the cpu needs to be notified directly. following reset, or master clear, the value stored for this bit is 0, and irq13 is selected. bit 6 must be settoa1to enable this bit during an s-g command register write. when bit 6 i s a 0 during the write, bit 7 will not have any effect on the current eop/irq13 selection. 6 enable irq13/eop programming: enabling irq13/eop programming allows initialization or modification of the s-g termination handling bits. if bit 5 is reset to 0, bit 7 will not have any effect on the state of irq13 or eop assertion. when bit 5 is set to a 1, bit 7 determines the termination handling following a terminal count. 5:2 reserved 1:0 s-g command code bits [ 1:0 ] function 00 no s-g command operation is performed. bits [ 7:5 ] may still be used to program eop/ irq13 selection. 01 the start command initiates the scatter-gather process. immediately after the start command is issued a request is issued to fetch the initial buffer to fill the base register set in preparation for performing a transfer. the buffer prefetch request has the same priority with respect to other channels as the dreq it is associated with. within the channel, dreq is higher in priority than a prefetch request. 10 the stop command halts a scatter-gather transfer immediately. when a stop command is given, the terminate bit in the s-g status register and the dma channel mask bit are both set. 11 reserved the s-g status register contains information on the s-g transfer status. this register maintains dynamic status information on s-g transfer activity, the current and base buffer state, s-g transfer termination, and the end of the list indicator. 70
82374eb/82374SB 3.2.22 scagastescatter-gather status register register location: channels 0 0419hechannels 1 041ahechannels 2 041bhechannels 3 041dhechannels 5 041ehechannels 6 041fhechannels 7 default value: 08h attribute: read only, relocatable size: 8 bits the scatter-gather status register provides scatter-gather process status information to the cpu or master. an active bit is set to 1 after the s-g start command is issued. the active bit will be 0 before the initial start command, following a terminal count, and after an s-g stop command is issued. the current buffer and base buffer state bits indicate whether the corresponding register has a buffer loaded. it is possible for the base buffer state to be set while the current buffer state is cleared. when the current buffer transfer is complete, the base buffer will not be moved into the current buffer until the start of the next data transfer. thus, the current buffer state is empty (cleared), while the base buffer state is full (set). the terminate bit is set active after a stop command, after tc for the last buffer in the list and both base and current buffers have expired. the eop and irq13 bits indicate which end of process indicator will be used to alert the system of an s-g process termination. the eol status bit is set if dma controller has loaded the last buffer of the link list. bit description 7 next link null indicator: if the next sgd fetched from memory during a fetch operation has the eol value (1), the current value of the next link register is not overwritten. instead, bit 7 of the channel's s-g status register, the next link null indicator, is set to a 1. if the fetch returns a eol value not equal to (1), this bit is reset to 0. this status bit is written after every fetch operation. following reset, or master clear, this bit is reset to 0. this bit is also cleared by an s-g start command write. 6 reserved 5 irq13 or eop on last buffer: when the irq13/eop status bit is 1, eop was either defaulted to at reset or selected through the s-g command register as the s-g process termination indicator. eop will be issued to alert the system when a terminal count occurs or following the stop command. when this bit is returned as a 0, an irq13 will be issued to alert the cpu of this same status. 4 reserved 3 s-g base buffer state: when the base buffer status bit contains a 0, the base buffer is empty. when the base buffer status bit is set to 1, the base buffer has a buffer link loaded. note that the base buffer state may be set while the current buffer state is cleared. this condition occurs when the current buffer expires following a transfer; the base buffer will not be moved into the current register until the start of the next dma transfer. 2 s-g current buffer state: when the current buffer status bit contains a 0, the current buffer is empty. when the current buffer status bit is set to 1, the current buffer has a buffer link loaded and is considered full. following reset, bit 2 is reset to 0. 1 reserved 71
82374eb/82374SB bit description 0 s-g active: the scatter-gather active bit indicates the current s-g transfer status. bit 0 will be a 1 after a s-g start command is issued. bit 0 will b e a 0 before the start command is issued. bit 0 will be a 0 after terminal count on the last buffer on the channel is reached. bit 0 will also b e a 0 after a s-g stop command has been issued. following reset, or master clear, this bit is reset to 0. 3.2.23 scagadescatter-gather descriptor table pointer register register location: 0420h 0423hechannels 0 0424h 0424hechannels 1 0428h 042bhechannels 2 042ch 042chechannels 3 0434h 0437hechannels 5 0438h 043bhechannels 6 043ch 043fhechannels 7 default value: see below attribute: read/write, relocateable size: 32 bits the sgd table pointer register contains the 32 bit pointer to the first sgd entry in the sgd table in memory. before the start of a s-g transfer, this register should have been programmed to point to the first sgd in the sgd table. following a ``start'' command, it initiates reading the first sgd entry by pointing to the first sgd entry to be fetched from the memory. subsequently, at the end of the each buffer block transfer, the contents of the sgd table pointer registers are incremented by 8 until the end of the sgd table is reached. when programmed by the cpu, the sgd table pointer registers can be programmed with a single 32-bit pci write. note that the pceb and eisa bus controller will split the 32-bit write into four 8-bit writes. following a prefetch to the address pointed to by the channel's sgd table pointer register, the new memory address is loaded into the base address register, the new byte count is loaded into the base byte count register, and the newly fetched next sgd replaces the current next sgd value. the end of the sgd table is indicated by a end of table field having a msb equal to 1. when this value is read during a sgd fetch, the current sgd value is not replaced. instead, bit 7 of the channel's status register is set to a 1 when the eol is read from memory. bit description 31:0 sgd table pointer: the sgd table pointer register contains a 32-bit pointer to the main memory location where the software maintains the scatter gather descriptors for the linked-list buffers. these bits are translated into a [ 31:0 ] signals for accessing memory on the pci. 72
82374eb/82374SB 3.2.24 cbpffeclear byte pointer flip flop register register location: 00chechannels 0-3 0d8hechannels 4-7 default value: xxh attribute: write only size: 8 bits this command is executed prior to writing or reading new address or word count information to the dma. this initializes the flip-flop to a known state so that subsequent accesses to register contents by the microproces- sor will address upper and lower bytes in the correct sequence. the clear byte pointer command clears the internal latch used to address the upper or lower byte of the 16-bit address and word count registers. the latch is also cleared at power on by reset and by the master clear command. the host cpu may read or write a 16-bit dma controller register by performing two consecutive accesses to the i/o port. the clear byte pointer command precedes the first access. the first i/o write to a register port loads the least significant byte, and the second access automatically accesses the most signifi- cant byte. when the host cpu is reading or writing dma registers, two byte pointer flip-flops are used; one for chan- nels 0-3 and one for channels 4-7. both of these act independently. there are separate software commands for clearing each of them (0ch for channels 0-3, 0d8h for channels 4-7). bit description 7:0 clear byte pointer ff: no specific pattern. command enabled with a write to the i/o port address. 3.2.25 dmcedma master clear register register location: 00dhechannels 0-3 0dahechannels 4-7 default value: xxh attribute: write only size: 8 bits this software instruction has the same effect as the hardware reset. the command, status, request, and internal first/last flip-flop registers are cleared and the mask register is set. the dma controller will enter the idle cycle. there are two independent master clear commands, 0dh which acts on channels 0-3, and 0dah which acts on channels 4-7. bit description 7:0 master clear: no specific pattern. command enabled with a write to the i/o port address. 73
82374eb/82374SB 3.2.26 dcmedma clear mask register register location: 00ehechannels 0-3 0dchechannels 4-7 default value: xxh attribute: write only size: n/a software command this command clears the mask bits of all four channels, enabling them to accept dma requests. i/o port 0eh is used for channels 0-3 and i/o port 0dch is used for channels 4-7. bit description 7:0 clear mask: no specific pattern. command enabled with a write to the i/o port address. 3.3 timer unit registers the esc contains five counters that are equivalent to those found in the 82c54 programmable interval timer. the timer registers control these counters and can be accessed from the eisa bus via i/o space. this section describes the counter/timer registers on the esc. the counter/timer operations are further described in section 8.0, interval timer 3.3.1 tcwetimer control word register register location: 043hetimer 1 04bhetimer 2 default value: xxh attribute: write only size: 8 bits the timer control word specifies the counter selection, the operating mode, the counter byte programming order and size of the count value, and whether it counts down in a 16-bit or binary-coded decimal (bcd) format. after writing the control word, a new count may be written at any time. the new value will take effect according to the programmed mode. there are six programmable counting modes. typically, the esc timer unit counters 0 and 2 are programmed for mode 3, the square wave mode, while counter 1 is programmed in mode 2, the rate generator mode. two special commands are selected through the control word register. the counter latch command is selected when bits [ 5:4 ] are both 0. the read-back command is selected when bits [ 7:6 ] are both 1. when either of these two commands are selected with the control word register, the meaning of the other bits in the register changes. both of these special commands, and the respective changes they make to the bit definitions in this register, are covered in detail under separate register descriptions later in this section. bits 4 and 5 are also used to select the count register programming mode. the programming process is simple: 1. write a control word. 2. write an initial count for each counter. 3. load the lsb, msb, or lsb then msb. the read/write selection chosen with the control word dictates the programming sequence that must follow when initializing the specified counter. 74
82374eb/82374SB if a counter is programmed to read/write two-byte counts, the following precaution applies: a program must not transfer control between writing the first and second byte to another routine which also writes into that same counter. otherwise, the counter will be loaded with an incorrect count. the count must always be completely loaded with both bytes. bits 6 and 7 are also used to select the counter for the control word you are writing. following reset, the control words for each register are undefined. you must program each timer to bring it into a known state. however, each counter out signal is reset to 0 following reset. the spkr output, interrupt controller input irq0 (internal), bit 5 of port 061h, and the internally generated refresh request are each reset to 0 following reset. bit description 7:6 counter select: the counter selection bits select the counter the control word acts upon as shown below. the read back command is selected when bits [ 7:6 ] are both 1. bit [ 7:6 ] function 00 counter 0 select 01 counter 1 select 10 counter 2 select 11 read back command (see section 3.3.2) 5:4 read/write select: bits [ 5:4 ] are the read/write control bits. the counter latch command is selected when bits [ 5:4 ] are both 0. the read/write options include read/write least significant byte, read/write most significant byte, or read/write the lsb and then the msb. the actual counter programming is done through the counter i/o port (040h, 041h, and 042h for counters 0, 1, and 2, respectively). bit [ 5:4 ] function 00 counter latch command (see section 3.3.3) 01 r/w least significant byte (lsb) 10 r/w most significant byte (msb) 11 r/w lsb then msb 3:1 counter mode selection: bits [ 3:1 ] select one of six possible modes of operation for the counter as shown below. note that for the fail safe timer (timer 2, counter 0), modes 1, 2, 3, 4, and 5 are reserved. bit [ 3:1 ] mode function 000 0 out signal on end of count ( e 0) 001 1 hardware retriggerable one-shot (reserved for timer 2, counter 0.) x10 2 rate generator (divide by n counter) (reserved for timer 2, counter 0.) x11 3 square wave output (reserved for timer 2, counter 0.) 100 4 software triggered strobe (reserved for timer 2, counter 0.) 101 5 hardware triggered strobe (reserved for timer 2, counter 0.) 0 binary/bcd countdown select: when bit 0 e 0, a binary countdown is used. the largest possible binary count is 2 16 . when bit 0 e 1, a binary coded decimal (bcd) count is used. the largest bcd count allowed is 104. 75
82374eb/82374SB 3.3.2 timer read back command register register location: 043hetimer 1 04bhetimer 2 default value: xxh attribute: write only size: 8 bits the read-back command is used to determine the count value, programmed mode, and current states of the out pin and null count flag of the selected counter or counters. the read-back command is written to the control word register, which latches the current states of the above mentioned variables. the value of the counter and its status may then be read by i/o access to the counter address. status and/or count may be latched on one, two, or all three of the counters by selecting the counter during the write. the count latched will stay latched until read, regardless of further latch commands. the count must be read before newer latch commands latch a new count. the status latched by the read-back command will also remain latched until after a read to the counter's i/o port. to reiterate, the status and count are unlatched only after a counter read of the status register, the count register, or the status and count register in succession. both count and status of the selected counter(s) may be latched simultaneously by setting both the count y and status y bits [ 5:4 ] e 00b. this is functionally the same as issuing two consecutive, separate read-back commands. as stated above, if multiple count and/or status read-back commands are issued to the same counter(s) without any intervening reads, all but the first are ignored. if both count and status of a counter are latched, the first read operation from that counter will return the latched status, regardless of which was latched first. the next one or two reads (depending on whether the counter is programmed for one or two byte counts) return the latched count. subsequent reads return an unlatched count. a register description of the status byte read follows later in this section. note that bit definitions for a write to this port changed when the read-back command was selected, when compared to a normal control word write to this same port. bit description 7:6 read back command: when bits [ 7:6 ] are both 1, the read-back command is selected during a write to the control word. the normal meanings (mode, countdown, r/w select) of the bits in the control register at i/o address 043h change when the read-back command is selected. following the read- back command, i/o reads from the selected counter's i/o addresses produce the current latch status, the current latched count, or both if bits 4 and 5 are both 0. 5 latch status of selected counters: when bit 5 is a 1, the current count value of the selected counters will be latched. when bit 4 is a 0, the status will not be latched. 4 latch count of selected counters: when bit 4 is a 1, the status of the selected counters will be latched. when bit 4 is a 0, the status will not be latched. the status byte format is described in the next register description. 3 counter 2: counter 2 is selected for the latch command selected with bits 4 and 5 if bit 3 is a 1. if bit 3 is a 0, status and/or count will not be latched. 2 counter 1: counter 1 is selected for the latch command selected with bits 4 and 5 if bit 2 is a 1. if bit 2 is a 0, status and/or count will not be latched. 1 counter 0: counter 0 is selected for the latch command selected with bits 4 and 5 if bit 1 is a 1. if bit 1 is a 0, status and/or count will not be latched. 0 reserved: must be 0. 76
82374eb/82374SB 3.3.3 counter latch command register register location: 043hetimer 1 04bhetimer 2 default value: xxh attribute: write only size: 8 bits the counter latch command latches the current count value at the time the command is received. this command is used to insure that the count read from the counter is accurate (particularly when reading a two- byte count). the count value is then read from each counter's count register. one, two or all three counters may be latched with one counter latch command. if a counter is latched once and then, some time later, latched again before the count is read, the second counter latch command is ignored. the count read will be the count at the time the first counter latch command was issued. the count must be read according to the programmed format. specifically, if the counter is programmed for two byte counts, two bytes must be read. the two bytes do not have to be read one right after the other; read, write, or programming operations for other counters may be inserted between them. one precaution is worth noting. if a counter is programmed to read/write two-byte counts, a program must not transfer control between reading the first and second byte to another routine which also reads from that same counter. otherwise, an incorrect count will be read. finish reading the latched two-byte count before transfer- ring control to another routine. note that bit definitions for a write to this port have changed when the read-back command was selected, when compared to a normal control word write to this same port. bit description 7:6 counter selection: bits 6 and 7 are used to select the counter for latching. bit [ 7:6 ] function 00 latch counter 0 select 01 latch counter 1 select 10 latch counter 2 select 11 read back command select 5:4 specifies counter latch command: when bits [ 5:4 ] are both 0, the counter latch command is selected during a write to the control word. the normal meanings (mode, countdown, r/w select) of the bits in the control register at i/o address 043h change when the counter latch command is selected. following the counter latch command, i/o reads from the selected counter's i/o addresses produce the current latched count. 3:0 reserved: must be 0. 77
82374eb/82374SB 3.3.4 tmstatetimer status byte format register register location: 040hetimer 1, counter 0 041hetimer 1, counter 1 042hetimer 1, counter 2 048hetimer 2, counter 0 04ahetimer 2, counter 2 default value: 0xxxxxxxb attribute: read only size: 8 bits per counter each counter's status byte may be read following an timer read-back command. the read-back command is programmed through the counter control register. if ``latch status'' is chosen as a read-back option for a given counter, the next read from the counter's i/o port address returns the status byte. the status byte returns the countdown type, either bcd or binary; the counter operational mode; the read/ write selection status; the null count, also referred to as the count register status; and the current state of the counter out pin. bit description 7 counter out pin state: when this bit is a 1, the out pin of the counter is also a 1. when this bit is a 0, the out pin of the counter is also a 0. 6 count register status: also referred to as null count, indicates when the last count written to the count register (cr) has been loaded into the counting element (ce). the exact time this happens depends on the counter mode and is described in the mode definitions, but until the count is loaded into the counting element (ce), it can't be read from the counter. if the count is latched or read before the load time, the count value returned will not reflect the new count written to the register. when bit 6 is a 0, the count has been transferred from cr to ce and is available for reading. when bit 6 is a 1, the null count condition exists. the count has not been transferred from cr to ce and is not yet available for reading. 5:4 read/write status: bits [ 5:4 ] reflect the read/write selection made through bits [ 5:4 ] of the control register. the binary codes returned during the status read match the codes used to program the counter read/write selection. 3:1 mode selection status: bits [ 3:1 ] return the counter mode programming. the binary code returned matches the code used to program the counter mode, as listed under the bit function above. 0 countdown type status: bit 0 reflects the current countdown type, either 0 for binary countdown or a 1 for binary coded decimal (bcd) countdown. 78
82374eb/82374SB 3.3.5 capsecounter access ports register location: 040hetimer 1, counter 0 041hetimer 1, counter 1 042hetimer 1, counter 2 048hetimer 2, counter 0 04ahetimer 2, counter 2 default value: xxh attribute: read/write size: 8 bits per counter each of these i/o ports is used for writing count values to the count registers; reading the current count value from the counter by either an i/o read, after a counter-latch command, or after a read-back command; and reading the status byte following a read-back command. bit description 7:0 counter access: each counter i/o port address is used to program the 16 bit count register. the order of programming, either lsb only, msb only, or lsb then msb, is defined with the counter control register at i/o port address 043h. the counter i/o port is also used to read the current count from the count register, and return the status of the counter programming following a read-back command. 3.4 interrupt controller registers the esc contains an eisa compatible interrupt controller that incorporates the functionality of two 82c59 interrupt controllers. the interrupt registers control the operation of the interrupt controller and can be ac- cessed from the eisa bus via i/o space. this section describes the interrupt registers. the operation of the interrupt controller is described in chapter 9.0. 3.4.1 icw1einitialization command word 1 register location: 020heint cntrl-1 0a0heint cntrl-2 default value: xxh attribute: write only size: 8 bits per controller a write to initialization command word one starts the interrupt controller initialization sequence. addresses 020h and 0a0h are referred to as the base addresses of cntrl-1 and cntrl-2 respectively. an i/o write to the cntrl-1 or cntrl-2 base address with bit 4 equal to 1 is interpreted as icw1. for esc- based eisa systems, three i/o writes to ``base address a 1'' must follow the icw1. the first write to ``base address a 1'' performs icw2, the second write performs icw3, and the third write performs icw4. 79
82374eb/82374SB icw1 starts the initialization sequence during which the following automatically occur: a. the edge sense circuit is reset, which means that following initialization, an interrupt request (irq) input must make a low-to-high transition to generate an interrupt. b. the interrupt mask register is cleared. c. irq7 input is assigned priority 7. d. the slave mode address is set to 7. e. special mask mode is cleared and status read is set to irr. f. if ic4 was set to 0, then all functions selected by icw4 are set to zero. however, icw4 must be programmed in the esc implementation of this interrupt controller, and ic4 must be set to a 1. icw1 has three significant functions within the esc interrupt controller configuration. icw4 is needed, so bit 0 must be programmed to a 1. there are two interrupt controllers in the system, so bit 1, sngl, must be programmed t oa0on both cntrl-1 and cntrl-2, to indicate a cascade configuration. bit 4 must be a 1 when programming icw1. ocw2 and ocw3 are also addressed at the same port as icw1. this bit indicates that icw1, and not ocw2 or ocw3, will be programmed during the write to this port. bit 2, adi, and bits [ 7:5 ] , a7-a5, are specific to an msc-85 implementation. these bits are not used by the esc interrupt controllers. bits [ 7:5,2 ] should each be initialized to 0. bit description 7:5 reserved: a7-a5 are mcs-85 implementation specific bits. they are not needed by the esc. these bits should be 000b when programming the esc. 4 icw/ocw select: bit 4 must b ea1to select icw1. after the fixed initialization sequence to icw1, icw2, icw3, and icw4, the controller base address is used to write to ocw2 and ocw3. bit 4 is a 0 on writes to these registers .a1on this bit at any time will force the interrupt controller to interpret the write as an icw1. the controller will then expect to see icw2, icw3, and icw4. 3 reserved: this bit is not used in the esc. 2 reserved: adi ignored for the esc. 1 sngl: this bit must be programmed t oa0to indicate that two interrupt controllers are operating in cascade mode on the esc. 0 ic4: this bit must be set to a 1. ic4 indicates that icw4 needs to be programmed. the esc requires that icw4 be programmed to indicate that the controllers are operating in an 80x86 type system. 80
82374eb/82374SB 3.4.2 icw2einitialization command word 2 register location: 021heint cntrl-1 0a1heint cntrl-2i default value: xxh attribute: write only size: 8 bits per controller icw2 is used to initialize the interrupt controller with the five most significant bits of the interrupt vector address. the value programmed for bits [ 7:3 ] is used by the cpu to define the base address in the interrupt vector table for the interrupt routines associated with each irq on the controller. typical isa icw2 values are 04h for cntrl-1 and 70h for cntrl-2. section 9.8.1 of the interrupt unit functional description contains a table detailing the interrupt vectors for each interrupt request level, as they would appear when the vector is driven onto the data bus. bit description 7:3 interrupt vector base address: bits [ 7:3 ] define the base address in the interrupt vector table for the interrupt routines associated with each interrupt request level input. for cntrl-1, a typical value is 00001b, and for cntrl-2, 10000b. the interrupt controller combines a binary code representing the interrupt level to receive service with this base address to form the interrupt vector that is driven out onto the bus. for example, the complete interrupt vector for irq [ 0 ] (cntrl-1), would be 0000 1000b (cntrl-1 [ 7:3 ] e 00001b and 000b representing irq [ 0 ] ). this vector is used by the cpu to point to the address information that defines the start of the interrupt routine. 2:0 interrupt request level: when writing icw2, these bits should all be 0. during an interrupt acknowledge cycle, these bits will be programmed by the interrupt controller with the interrupt code representing the interrupt level to be serviced. this interrupt code is combined with bits [ 7:3 ] to form the complete interrupt vector driven onto the data bus during the second inta y cycle. the table in section 9.8.1 outlines each of these codes. the code is a simple three bit binary code: 000b represents irq0 (irq8), 001b irq1 (irq9), 010b irq2 (irq10), and so on until 111b irq7 (irq15). 81
82374eb/82374SB 3.4.3 icw3einitialization command word 3 (master) register location: 021heint cntrl-1 default value: xxh attribute: write only size: 8 bits the meaning of icw3 differs between cntrl-1 and cntrl-2. on cntrl-1, the master controller, icw3 indicates which cntrl-1 irq line physically connects the int output of cntrl-2 to cntrl-1. icw3 must be programmed to 04h, indicating the cascade of the cntrl-2 int output to the irq [ 2 ] input of cntrl-1. an interrupt request on irq2 causes cntrl-1 to enable cntrl-2 to present the interrupt vector address during the second interrupt acknowledge cycle. bit description 7:3, cascade interrupt controller irqs: bits [ 7:3 ] and bits [ 1:0 ] must be programmed to 0. 1:0 2 cascade interrupt controller irqs: bit 2 must always be programmed to a 1. this bit indicates that cntrl-2, the slave controller, is cascaded on interrupt request line two (irq [ 2 ] ). when an interrupt request is asserted to cntrl-2, the irq goes through the priority resolver. after the slave controller priority resolution is finished, the int output of cntrl-2 is asserted. however, this int assertion does not go directly to the cpu. instead, the int assertion cascades into irq [ 2 ] on cntrl-1. irq [ 2 ] must go through the priority resolution process on cntrl-1. if it wins the priority resolution on cntrl-1 and the cntrl-1 int signal is asserted to the cpu, the returning interrupt acknowledge cycle is really destined for cntrl-2. the interrupt was originally requested at cntrl-2, so the interrupt acknowledge is destined for cntrl-2, and not a response for irq [ 2 ] on cntrl-1. when an interrupt request from irq [ 2 ] wins the priority arbitration, in reality an interrupt from cntrl-2 has won the arbitration. because bit 2 of icw3 on the master is set to 1, the master knows which identification code to broadcast on the internal cascade lines, alerting the slave controller that it is responsible for driving the interrupt vector during the second inta y pulse. 3.4.4 icw3einitialization command word 3 (slave) register location: int cntrl-2 port address-0a1h default value: xxh attribute: write only size: 8 bits on cntrl-2 (the slave controller), icw3 is the slave identification code broadcast by cntrl-1 from the trailing edge of the first inta y pulse to the trailing edge of the second inta y pulse. cntrl-2 compares the value programmed in icw3 with the incoming identification code. the code is broadcast over three esc internal cascade lines. icw3 must be programmed to 02h for cntrl-2. when 010b is broadcast by cntrl-1 during the inta y sequence, cntrl-2 assumes responsibility for broadcasting the interrupt vector during the second interrupt acknowledge cycle. as an illustration, consider an interrupt request on irq [ 2 ] of cntrl-1. by definition, a request on irq [ 2 ] must have been asserted by cntrl-2. if irq [ 2 ] wins the priority resolution on cntrl-1, the interrupt acknowledge cycle returned by the cpu following the interrupt is destined for cntrl-2, not cntrl-1. cntrl-1 will see the inta y signal, and knowing that the actual destination is cntrl-2, will broadcast a slave identification code across the internal cascade lines. cntrl-2 will compare this incoming value with the 010b stored in icw3. following a positive decode of the incoming message from cntrl-1, cntrl-2 will drive the appropriate interrupt vector onto the data bus during the second interrupt acknowledge cycle. 82
82374eb/82374SB bit description 7:3 reserved: must be 0. 2:0 slave identification code: the slave identification code must be programmed to 010b during the initialization sequence. the code stored in icw3 is compared to the incoming slave identification code broadcast by the master controller during interrupt acknowledge cycles. 3.4.5 icw4einitialization command word 4 register location: 021heint cntrl-1 0a1heint cntrl-2 default value: xxh attribute: write only size: 8 bits both esc interrupt controllers must have icw4 programmed as part of their initialization sequence. minimally, the microprocessor mode bit, bit 0, must be set to a 1 to indicate to the controller that it is operating in an 80x86 based system. failure to program this bit will result in improper controller operation during interrupt acknowledge cycles. additionally, the automatic end of interrupt (aeoi) may be selected, as well as the special fully nested mode (sfnm) of operation. the default programming for icw4 is 01h, which selects 80x86 mode, normal eoi, buffered mode, and special fully nested mode disabled. bits 2 and 3 must be programmed to 0 for the esc interrupt unit to function correctly. both bit 1, aeoi, and bit 4, sfnm, can be programmed if the system developer chooses to invoke either mode. bit description 7:5 reserved: must be 0. 4 sfnm: bit 4, sfnm, should normally be disabled by writin ga0to this bit. if sfnm e 1, the special fully nested mode is programmed. 3:2 master/slave buffer mode (buf): bit 3, buf, must be programmed to 0 for the esc. this is non- buffered mode. while different programming options are sometimes offered for bits 2 and 3, within the esc interrupt unit, bits 2 and 3 must always be programmed to 00b. 1 aeoi: bit 1, aeoi, should normally be programmed to 0. this is the normal end of interrupt. if aeoi e 1, the automatic end of interrupt mode is programmed. 0 microprocessor mode: the microprocessor mode bit must be programmed to 1 to indicate that the interrupt controller is operating in an 80x86 based system. never program this bit to 0. 83
82374eb/82374SB 3.4.6 ocw1eoperation control word 1 register location: 021heint cntrl-1 0a1heint cntrl-2 default value: xxh attribute: read/write size: 8 bits ocw1 sets and clears the mask bits in the interrupt mask register (imr). each interrupt request line may be selectively masked or unmasked any time after initialization. a single byte is written to this register. each bit position in the byte represents the same-numbered channel: bit 0 e irq [ 0 ] , bit 1 e irq [ 1 ] and so on. setting the bit to a 1 sets the mask, and clearing the bit to a 0 clears the mask. note that masking irq [ 2 ] on cntrl-1 will also mask all of controller 2's interrupt requests (irq8-irq15). reading ocw1 returns the controller's mask register status. the imr stores the bits which mask the interrupt lines to be masked. the imr operates on the irr. masking of a higher priority input will not effect the interrupt request lines of lower priority. unlike status reads of the isr and irr, for reading the imr, no ocw3 is needed. the output data bus will contain the imr whenever i/o read is active and the i/o port address is 021h or 0a1h (ocw1). all writes to ocw1 must occur following the icw1-icw4 initialization sequence, since the same i/o ports are used for ocw1, icw2, icw3 and icw4. bit description 7:0 interrupt request mask: whena1is written to any bit in this register, the corresponding irq [ x ] line is masked. for example, if bit 4 is set to a 1, then irq [ 4 ] will be masked. interrupt requests on irq [ 4 ] will not set channel 4's interrupt request register (irr) bit as long as the channel is masked. whena0is written to any bit in this register, the corresponding irq [ x ] mask bit is cleared, and interrupt requests will again be accepted by the controller. note that masking irq [ 2 ] on cntrl-1 will also mask the interrupt requests from cntrl-2, which is physically cascaded to irq [ 2 ] . 3.4.7 ocw2eoperation control word 2 register location: 020heint cntrl-1 0a0heint cntrl-2 default value: xxh attribute: write only size: 8 bits ocw2 controls both the rotate mode and the end of interrupt mode, and combinations of the two. the three high order bits in an ocw2 write represent the encoded command. the three low order bits are used to select individual interrupt channels during three of the seven commands. the three low order bits (labeled l2, l1 and l0) are used when bit 6, the sl bit, is set to a 1 during the command. following a reset and icw initialization, the controller enters the fully nested mode of operation. non-specific eoi without rotation is the default. both rotation mode and specific eoi mode are disabled following initializa- tion. 84
82374eb/82374SB bit description 7:5 rotate and eoi codes (r, sl, eoi): these three bits control the rotate and end of interrupt modes and combinations of the two. a chart of these combinations is listed above under the bit definition. bits [ 7:5 ] function 001 non-specific eoi command 011 specific eoi command 101 rotate on non-specific eoi command 100 rotate in auto eoi mode (set) 000 rotate in auto eoi mode (clear) 111 * rotate on specific eoi command 110 * set priority command 010 no operation * l0 - l2 are used 4:3 ocw2 select: when selecting ocw2, bits 3 and 4 must both be 0. if bit 4 is a 1, the interrupt controller interprets the write to this port as an icw1. therefore, always ensure that these bits are both 0 when writing an ocw2. 2:0 interrupt level select (l2, l1, l0): l2, l1, and l0 determine the interrupt level acted upon when the sl bit is active. a simple binary code, outlined above, selects the channel for the command to act upon. when the sl bit is inactive, these bits do not have a defined function; programming l2, l1 and l0 to 0 is sufficient in this case. bit [ 2:0 ] interrupt level 000 irq 0(8) 001 irq 1(9) 010 irq 2(10) 011 irq 3(11) 100 irq 4(12) 101 irq 5(13) 110 irq 6(14) 111 irq 7(15) 3.4.8 ocw3eoperation control word 3 register location: 020heint cntrl-1 0a0heint cntrl-2 default value: x01xxx10b attribute: read/write size: 8 bits ocw3 serves three important functions; enable special mask mode, poll mode control, and irr/isr register read control. first, ocw3 is used to set or reset the special mask mode (smm). the special mask mode can be used by an interrupt service routine to dynamically alter the system priority structure while the routine is executing, through selective enabling/disabling of the other channel's mask bits. second, the poll mode is enabled when a write to ocw3 is issued with bit 2 equal to 1. the next i/o read to the interrupt controller is treated like an interrupt acknowledge; a binary code representing the highest priority level interrupt request is released onto the bus. 85
82374eb/82374SB third, ocw3 provides control for reading the in-service register (isr) and the interrupt request register (irr). either the isr or irr is selected for reading with a write to ocw3. bits 0 and 1 carry the encoded command to select either register. the next i/o read to the ocw3 port address will return the register status specified during the previous write. the register specified for a status read is retained by the interrupt control- ler. therefore, a write to ocw3 prior to every status read command is unnecessary, provided the status read desired is from the register selected with the last ocw3 write. bit description 7 reserved: must be 0. 6 smm: if esmm e 1 and smm e 1 the interrupt controller will enter special mask mode. if esmm e 1 and smm e 0 the interrupt controller will revert to normal mask mode. when esmm e 0, smm has no effect. 5 enable special mask mode: when this bit is set to 1 it enables the smm bit to set or reset the special mask mode. when esmm e 0 the smm bit becomes a ``don't care''. 4:3 ocw3 select: when selecting ocw3, bit 3 must b e a 1 and bit 4 must be 0. if bit 4 is a 1, the interrupt controller interprets the write to this port as an icw1. therefore, always ensure that bits [ 4:3 ] are ``01b'' when writing an ocw3. 2 poll mode command: when bit 2 is a 0, the poll command is not issued. when bit 2 is a 1, the next i/o read to the interrupt controller is treated as an interrupt acknowledge cycle. an encoded byte is driven onto the data bus, representing the highest priority level requesting service. 1:0 register read command: bits [ 1:0 ] provide control for reading the in-service register (isr) and the interrupt request register (irr). when bit 1 e 0, bit 0 will not effect the register read selection. when bit 1 e 1, bit 0 selects the register status returned following an ocw3 read. if bit 0 e 0, the irr will be read. if bit 0 e 1, the isr will be read. following icw initialization, the default ocw3 port address read will be ``read irr''. to retain the current selection (read isr or read irr), always writ ea0tobit1 when programming this register. the selected register can be read repeatedly without reprogramming ocw3. to select a new status register, ocw3 must be reprogrammed prior to attempting the read. bits [ 1:0 ] function 00 no action 01 no action 10 read irq register 11 read is register 86
82374eb/82374SB 3.4.9 elcreedge/level control register register location: 04d0heint cntrl-1 04d1heint cntrl-1 default value: 00h attribute: read/write size: 8 bits the edge/level control register is used to set the interrupts to be triggered by either the signal edge or the logic level. int0, int1, int2, int8, int13 must be set to edge sensitive. after a reset all the int signals are set to edge sensitive. programming considerations: if an interrupt is switched from level to edge sensitive, a false interrupt is generated on that interrupt line. if the irqx line is high, then switching the level/edge bet from a 1 to a 0 causes the interrupt controller to detect an interrupt. also note that even if this interrupt is masked when programming this register, the interrupt controller still latches the false interrupt. as soon as this interrupt is unmasked, the false interrupt is processed. thus, before switching the edge/level function, disable interrupts to the processor (either mask interrupts or cli instruction). then program the elcr register. finally, re-initialize the interrupt controller to clear the false interrupt. bit description 7:0 edge/level select: the bits select if the interrupts are triggered by either the signal edge or the logic level . a 0 bit represents an edge sensitive interrupt, an da1isfor level sensitive. bit [ 2:0 ] and bit 13 must be set to 0. after a reset or power-on these registers are set to 00h. bit port 04d0h port 04d1h 0 int0 int8 1 int1 int9 2 int2 int10 3 int3 int11 4 int4 int12 5 int5 int13 6 int6 int14 7 int7 int15 3.4.10 nmiscenmi status and control register register location: 061h default value: x0x0 0000 attribute: read/write, read only size: 8 bits this register is used to check the status of different system components, control the output of the speaker counter (timer 1, counter 2), and gate the counter output that drives the spkr signal. this register also controls nmi generation and reports nmi source status. note that nmi generation is globally enabled/disabled via the nmiertc register and nmi generation for serr y is controlled via the ms register. bits [ 7:4 ] of this register are read-only and must be written as 0s when writing to this register. bits [ 3:0 ] are read/write. follow- ing reset, bit 7 returns the pci system board parity error status (perr y ) and bit 5 is undetermined until counter 2 is properly programmed. 87
82374eb/82374SB bit description 7 system board errorero: bit 7 is set if the perr y line is pulsed. this interrupt is enabled by setting bit 2 to 0. to reset the interrupt, set bit 2 to 0 and then set it to 1. note that this bit does not reflect status of an nmi caused by serr y , which is enabled and disabled/cleared via the ms register. 6 iochk y nmi sourceero: bit 6 is set if an expansion board asserts iochk y on the isa/eisa bus. this interrupt is enabled by setting bit 3 to 0. to reset the interrupt, set bit 3 to 0 and then set it to 1. 5 timer 1, counter 2ero: the timer 1, counter 2 out signal state is reflected in bit 5. the value on this bit following a read is the current state of the counter 2 out signal. counter 2 must be programmed following a reset for this bit to have a determinate value. 4 refresh cycle toggleero: the refresh cycle toggle signal toggles from either 0 to 1 or 1 to 0 following every refresh cycle. 3 iochk y nmi enableer/w: when bit 3 is a 1, iochk y nmi's are disabled and cleared, and when bit 3 is a 0 (default), iochk y nmi's are enabled. 2 pci system board errorer/w: when bit 2 is a 1, the system board error is disabled and cleared. when bit 2 i s a 0 (default), the system board parity error is enabled. note that nmi generation for system board errors is enabled/disabled via bit 3 (system error) of the mode select register. following reset, bit 2 is a 0, and system board errors are enabled. 1 speaker data enableer/w: speaker data enable is anded with the timer 1, counter 2 out signal to drive the spkr output signal. when bit 1 i s a 0 (default), the result of the and is always 0 and the spkr output is always 0. when bit 1 is a 1, the spkr output is equivalent to the counter 2 out signal value. 0 timer 1, counter 2 gate enableer/w: when bit 0 is a 0, timer 1, counter 2 counting is disabled. counting is enabled when bit 0 is a 1. this bit controls the gate input to counter 2. 3.4.11 nmiertcenmi control and real-time clock address register location: 070h default value: see below attribute: write only size: 8 bits the most-significant bit enables or disables all nmi sources including perr y , serr y , iochk y , fail-safe timer, bus timeout, and the nmi port. write an 80h to the nmiertc register to mask the nmi signal. this register is shared with the real-time clock. the real-time-clock uses the lower six bits of this port to address memory locations. writing to port 70h sets both the enable/disable bit and the memory address pointer. do not modify the contents of this register without considering the effects on the state of the other bits. bit description 7 nmi enable: setting bit 7 t o a 1 will disable all nmi sources. setting the bit t o a 0 enables the nmi interrupt. 6:0 real-time clock address: used by the real-time clock on the base i/o component to address memory locations. not used for nmi enabling/disabling. 88
82374eb/82374SB 3.4.12 nmiescenmi extended status and control register register location: 0461h default value: see below attribute: read/write, read only size: 8 bits this register is used to check the status of different system components, control the output of the speaker counter (timer 1, counter 2), and gate the counter output that drives the spkr signal. bits 4, 5, 6, and 7 are read-only. bits 0-3 are both read and write. when writing to this port, these bits must be written as 0's. bit 7 returns the fail-safe timer status. this input comes from timer 2, counter 0. the current status of bit 2 enables or disables this fail-safe timer nmi source. bit 6 returns the bus timeout status. bit 6 is set if either a 64 bclk or a 256 bclk occurs. the current status of bit 3 enables or disables this fail-safe timer nmi source. if nmi is caused by a bus timeout, bit 4 distinguished between the 8 m s (64 bclk) and 32 m s (256 bclk) timeout. bit 5 is the current state of an i/o write to port 0462h. the current status of bit 1 enables or disables software generated nmi. bit 0 controls the state of the rstdrv output signal. if bit 0 is set to 1, the rstdrv signal is asserted and a system bus reset is performed. bit 0 should be set long enough ( l 8 bclks) for the system bus devices to be properly reset. bit description 7 fail-safe timer statusero: this bit indicates the status of the fail-safe timer. when timer 2, counter 0 count expires, this bit is set t oa1ifbit2has previously been set to 1. a value of 0 indicates that the current nmi was not caused by the fail-safe timer. a value of 1 indicates that the fail-safe timer has timed out. 6 bus timeout statusero: this bit indicates the status of bus master timeout logic. if this bit is 0, the bus master timeout logic has not detected a bus timeout. if this bit is 1, the bus master timeout logic has detected a bus timeout. 5 software nmi statusero: this bit indicates the status of the software nmi port writes. a write to i/o port 0462 of any value will set this bit to 1 if bit 1 is set to 1. if this bit is 0, the current nmi was not caused by a write to the nmi port. if this bit is 1, the current nmi was caused by a write to the nmi port. 4 bus timeout statusero: this bit indicates the status of the 8 m s eisa bus master timeout event. if the bit is 0, the current nmi was not caused by the 8 m s eisa bus master timeout. if this bit is 1, the current nmi was caused by this bus timeout. 3 bus timeout enableer/w: this bit enables/disables nmi eisa bus timeout. if this bit is 0, an nmi will not be generated for bus timeout. also the nmi condition caused by the bus timeout will be cleared. if this bit is 1 an nmi will be generated when timer 2 counter 0 count expires. 2 fail-safe nmi enableer/w: this bit enables/disables nmi when the fail-safe timer timesout. if this bit is 0, an nmi will not be generated when the timer 2 counter 0 count expires. also the nmi condition caused by the fail-safe timer will be cleared. if this bit is 1 an nmi will be generated when timer 2 counter 0 count expires. 1 software nmi enableer/w: this bit enables/disables software generated nmi. if this bit is 0, a write to i/o port 0462h will not generate an nmi. if this bit is 1 nmi will be generated for a write to i/o port 0462h. 0 bus reseter/w: when bit 0 is a 0, rstdrv signal function as a normal reset drive signal. when bit 0 is 1, the rstdrv signal is asserted. following reset, bit 0 i s a 0 and the rstdrv output is low. 89
82374eb/82374SB 3.4.13 softnmiesoftware nmi generation register register location: 0462h default value: xxh attribute: write only size: 8 bits a write to this port with any data will cause an nmi. this port provides a software mechanism to cause an nmi if interrupts are enabled. bit description 7:0 software nmi port: the bit pattern is not specific. a write to this port will generate a software nmi if enabled. 3.5 eisa configuration, floppy support, and port 92h 3.5.1 conframpeconfiguration ram page register register location: 0c00h default value: xxx00000b attribute: read/write size: 8 bits this register contains the configuration ram page address. during accesses to the configuration ram (0800h 08ffh), the esc drivers the cpg [ 4:0 ] signals with the value of bits [ 4:0 ] of this register. the cpg [ 4:0 ] signals are connected to address pins addr [ 12:8 ] of the configuration ram. bit description 7:5 reserved 4:0 cram page address: the value of these bit selects a specific page from the configuration ram space. the sa [ 7:0 ] addresses select the location within this page during i/o accesses to the configuration ram. the value is driven onto cpg [ 4:0 ] during accesses to configuration ram. 3.5.2 digoutedigital output register register location: 03f2h (primary), 0372h (secondary) default value: xxxx0xxxb attribute: write only size: 8 bits this register is used to prevent xbusoe y from responding to dack2 y during a dma read access to a floppy controller on the isa bus. if a second floppy (residing on the isa bus) is using dack2 y in conjunction with a floppy on the x-bus, this prevents the floppy on the x-bus and the x-bus transceiver from responding to an access targeted for the floppy on the isa bus. this register is also located in the floppy controller device. 90
82374eb/82374SB bit description 7:4 not used: these bits exist in the 82077 fdc. refer to the 82077 data sheet for further details. 3 dma enable: when this bit is a 1, the assertion of dack y will result in xbusoe y being asserted. if this bit is 0, dack2 y has no effect on xbusoe y . this port bit also exists on the 82077 fdc. this bit defaults to disable (0). 2:0 not used: these bits exist in the 82077 fdc. refer to the 82077 data sheet for further details. 3.5.3 port 92 register register location: 92h default value: 00100100b attribute: read/write size: 8 bits this register is used to support the alternate reset (altrst y ), alternate a20 (alta20), power-on password protection, and fixed disk light function (dlight y ). this register is only accessible if bit 6 in the peripheral chip select enable b register is set to 1. bit description 7:6 fixed disk activity light: these bits are used to turn the fixed disk activity light on and off. when either of these bits are set to a 1, the light is turned on (dlight y driven active). to turn the light off, both of these bits must be 0. 5 reserved: this bit is reserved and will always retur n a 1 when read. 4 not used: this bit is not used and will always retur n a 0 when read. 3 power on password protection: a 1 on this bit enables power-on password protection by inhibiting accesses to the rtc memory for rtc addresses (port 70h) from 36h to 3fh. this is accomplished by not generating rtcrd y and rtcwr y signals for theses accesses. 2 reserved: this bit is reserved and will always retur n a 1 when read. 1 alta20 signal: writin ga0to this bit causes the alta20 signal to be driven low. writin ga1to this bit causes the alta20 signal to be driven high. 0 altrst y signal: this read/write bit provides an alternate system reset function. this function provides an alternate means to reset the system cpu to effect a mode switch from protected virtual address mode to the real address mode. this provides a faster means of reset than is provided by the keyboard controller. this bit is set t oa0bya system reset. writin ga1to this bit will cause the altrst y signal to pulse active (low) for approximately 4 sysclk's. before another altrst y pulse can be generated, this bit must be written back to a 0. 91
82374eb/82374SB 3.5.4 leisamgelast eisa bus master granted register register location: 0464h default value: xxh attribute: read only size: 8 bits this register contains information about which eisa bus master most recently had control of the eisa bus. a bit read of 0 indicates that the corresponding slot most recently was granted the bus. bit description 7:0 last eisa bus master: a value of 1 is placed in the bit position of the most recently granted eisa bus master. 3.6 power management registers this section describes two power management registers that are in the 82374SBapms and apmc registers. these registers are located in normal i/o space and must be accessed (via the cpu or pci bus) with 8-bit accesses. note that the rest of the power management registers are part of the esc configuration registers. 3.6.1 apmceadvanced power management control port i/o address: 0b2h default value: 00h attribute: read/write size: 8 bits this register passes data (apm commands) between the os and the smi handler. in addition, writes can generate an smi and reads can cause stpclk y to be asserted. the esc operation is not effected by the data in this register. bit description 7:0 apm control port (apmc): writes to this register store data in the apmc register and reads return the last data written. in addition, writes generate an smi, if bit 7 of the smien register and bit 0 of the smicntl register are both is set to 1. reads cause the stpclk y signal to be asserted, if bit 1 of the smicntl register is set to 1. reads do not generate an smi. 3.6.2 apmseadvanced power management status port i/o address: 0b3h default value: 00h attribute: read/write size: 8 bits this register passes status information between the os and the smi handler. the esc operation is not effected by the data in this register. bit description 7:0 apm status port (apms): writes store data in this register and reads return the last data written. 92
82374eb/82374SB 3.7 apic registers this section describes the registers used to program the advanced programmable interrupt controller. the i/o apic registers are accessed by an indirect addressing scheme using two registers (ioregsel and iowin) that are located in the cpu's memory space (memory address specified by the apicbase register). to reference an i/o apic register, a dword memory write loads the ioregsel register with a 32-bit value that specifies the apic register. the iowin register then becomes a four byte window pointing to the apic register specified by bits [ 7:0 ] of the ioregsel register. the register address table is shown in the address decode section. all apic registers are accessed using 32-bit loads and stores. this implies that to modify a field (e.g., bit, byte) in any register, the whole 32-bit register must be read, the field modified, and the 32-bits written back. in addition, registers that are described as 64-bits wide are accessed as multiple independent 32-bit registers. 3.7.1 ioregselei/o register select register memory address: fec0 x000h (82374eb) (x e see apicbase register) fec0 xy00h (82374SB) (xy e see apicbase register) default value: 00h attribute: read/write size: 32 bits this register selects an i/o apic unit register. the contents of the selected 32-bit register can be manipulated via the i/o window register. bit description 31:8 reserved 7:0 apic register address: bits [ 7:0 ] specify the apic register to be read/written via the iowin register. 3.7.2 iowinei/o window register memory address: fec0 x010h (82374eb) (x e see apicbase register) fec0 xy10h (82374SB) (xy e see apicbase register) default value: 00h attribute: read/write size: 32 bits this register is mapped onto the i/o unit's register selected by the ioregsel register. readability/writability by software is determined by the i/o apic register that is currently selected. bit description 31:0 apic register data: memory references to this register are mapped to the apic register specified by the contents of the ioregsel register. 93
82374eb/82374SB 3.7.3 apicidei/o apic identification register address offset: 00h default value: 00h attribute: read/write size: 32 bits this register contains the unit's 4-bit apic id. the id serves as a physical name of the i/o apic unit. all apic units using the apic bus should have a unique apic id. the apic bus arbitration id for the i/o unit is also writtten during a write to the apicid register (same data is loaded into both). this register must be pro- grammed with the correct id value before using the i/o apic unit for message transmission. bit description 31:28 reserved 27:24 i/o apic identification: this 4-bit field contains the i/o apic identification. 23:0 reserved 3.7.4 apicidei/o apic identification register address offset: 01h default value: 00h attribute: read only size: 32 bits the i/o apic version register identifies the apic hardware version. software can use this to provide compati- bility between different apic implementations and their versions. in addition, this register provides the maxi- mum number of entries in the i/o redirection table. bit description 31:24 reserved 23:16 maximum redirection entry: this field contains the entry number (0 being the lowest entry) of the highest entry in the i/o redirection table. the value is equal to the number of interrupt input pins minus one of this i/o apic. the range of values is 0 through 239. for the esc, this value is 0fh. 15:8 reserved 7:0 apic version: this 8 bit field identifies the implementation version. the version numbers are assigned for 82489dx and apic as follows: 0xh e 82489dx 1xh e apic 20 ffh e reserved for the esc, the current value is 11h. 94
82374eb/82374SB 3.7.5 apicarbei/o apic arbitration register address offset: 02h default value: 000f0011h attribute: read only size: 32 bits the apicarb register contains the bus arbitration priority for the i/o apic. this register is loaded whenever the i/o apic id register is written. bit description 31:28 reserved 27:24 i/o apic identification: this 4 bit field contains the i/o apic identification. 23:0 reserved 3.7.6 ioredtbl [ 15:0 ] ei/o redirection table registers address offset: 10-11h (ioredtbl0) 12-13h (ioredtbl1) 14-15h (ioredtbl2) 16-17h (ioredtbl3) 18-19h (ioredtbl4) 1a-1bh (ioredtbl5) 1c-1dh (ioredtbl6) 1e-1fh (ioredtbl7) 20-21h (ioredtbl8) 22-23h (ioredtbl9) 24-25h (ioredtbl10) 26-27h (ioredtbl11) 28-29h (ioredtbl12) 2a-2bh (ioredtbl13) 2c-2dh (ioredtbl14) 2e-2fh (ioredtbl15) default value: xx000000 00010xxxh attribute: read/write, read only size: 64 bits each there are 16 i/o redirection table entry registers. each register is a dedicated entry for each interrupt input pin. unlike irq pins of the 8259a, the notion of interrupt priority is completely unrelated to the position of the physical interrupt input pin on the apic. instead, software determines the vector (and therefore the priority) for each corresponding interrupt input pin. for each interrupt pin, the operating system can also specify the signal polarity (low active or high active), whether the interrupt is signaled as edges or levels, as well as the destina- tion and delivery mode of the interrupt. the information in the redirection table is used to translate the corresponding interrupt pin information into an inter-apic message. for a signal on an edge-sensitive interrupt input pin to be recognized as a valid edge (and not a glitch), the input level on the pin must remain asserted until the i/o apic unit broadcasts the corresponding message over the apic bus and the message has been accepted by the destination(s) specified in the destination field. only then will the source apic be able to recognize a new edge on that interrupt input pin. that new edge only results in a new invocation of the handler if its acceptance by the destination apic causes the interrupt request register bit to go from 0 to 1. (in other words, if the interrupt wasn't already pending at the destina- tion.) 95
82374eb/82374SB bit description 63:56 destination field: if the destination mode of this entry is physical mode (bit 11 e 0), bits [ 59:56 ] contain an apic id. if logical mode is selected (bit 11 e 1), the destination field potentially defines a set of processors. bits [ 63:56 ] of the destination field specify the logical destination address. 55:17 reserved 16 interrupt mask: when this bit is 1, the interrupt signal is masked. edge-sensitive interrupts signaled on a masked interrupt pin are ignored (i.e., not delivered or held pending). level-asserts or negates occurring on a masked level-sensitive pin are also ignored and have no side effects. changing the mask bit from unmasked to masked after the interrupt is accepted by a local apic has no effect on that interrupt. this behavior is identical to the case where the device withdraws the interrupt before that interrupt is posted to the processor. it is software's responsibility to handle the case where the mask bit is set after the interrupt message has been accepted by a local apic unit but before the interrupt is dispensed to the processor. when this bit is 0, the interrupt is not masked. an edge or level on an interrupt pin that is not masked results in the delivery of the interrupt to the destination. 15 trigger modeer/w: the trigger mode field indicates the type of signal on the interrupt pin that triggers an interrupt. this bit is set to 1 for level sensitive and 0 for edge sensitive. 14 remote irrero: this bit is used for level triggered interrupts. its meaning is undefined for edge triggered interrupts. for level triggered interrupts, this bit is set to 1 when local apic(s) accept the level interrupt sent by the i/o apic. the remote irr bit is set to 0 when an eoi message with a matching interrupt vector is received from a local apic. 13 interrupt input pin polarity (intpol)er/w: this bit specifies the polarity of the interrupt signal. a 0 selects high active an d a 1 selects low active. 12 delivery status (delivs)ero: the delivery status bit contains the current status of the delivery of this interrupt. delivery status is read-only and writes to this bit (as part of a 32 bit word) do not effect this bit. when bit 12 e 0 (idle), there is currently no activity for this interrupt. when bit 12 e 1 (send pending), the interrupt has been injected. however, its delivery is temporarily held up due to the apic bus being busy or the inability of the receiving apic unit to accept that interrupt at that time. 11 destination mode (destmod)er/w: this field determines the interpretation of the destination field. when destmod e 0 (physical mode), a destination apic is identified by its id. bits 56 through 59 of the destination field specify the 4 bit apic id. when destmod e 1 (logical mode), destinations are identified by matching on the logical destination under the control of the destination format register and logical destination register in each local apic. bits 56 through 63 (8 msb) of the destination field specify the 8 bit apic id. 96
82374eb/82374SB bit description 10:8 delivery mode (delmod)er/w: the delivery mode i s a 3 bit field that specifies how the apics listed in the destination field should act upon reception of this signal. note that certain delivery modes only operate as intended when used in conjunction with a specific trigger mode. these restrictions are indicated in the following table for each delivery mode. bits [ 10:8 ] mode description 000 fixed deliver the signal on the intr signal of all processor cores listed in the destination. trigger mode for ``fixed'' delivery mode can be edge or level. 001 lowest priority deliver the signal on the intr signal of the processor core that is executing at the lowest priority among all the processors listed in the specified destination. trigger mode for ``lowest priority''. delivery mode can be edge or level. 010 smi system management interrupt. a delivery mode equal to smi requires an edge trigger mode. the vector information is ignored but must be programmed to all zeroes for future compatibility. 011 reserved 100 nmi deliver the signal on the nmi signal of all processor cores listed in the destination. vector information is ignored. nmi must be programmed as edge-triggered for proper operation. 101 init deliver the signal to all processor cores listed in the destination by asserting the init signal. all addressed local apics will assume their init state. init must be programmed as edge-triggered for proper operation 110 reserved 111 extint deliver the signal to the intr signal of all processor cores listed in the destination as an interrupt that originated in an externally connected (8259a-compatible) interrupt controller. the inta cycle that corresponds to this extint delivery is routed to the external controller that is expected to supply the vector. a delivery mode of ``extint'' requires an edge trigger mode. 7:0 interrupt vector (intvec)er/w: the vector field is an 8 bit field containing the interrupt vector for this interrupt. vector values range from 10 to feh. 97
82374eb/82374SB 4.0 address decoding the esc contains an address decoder to decode eisa/isa master cycles. the esc address decoder uses the address line la [ 31:2 ] , and byte enable be [ 3:0 ] y to decode eisa master cycles. for isa master cycles, the esc uses address line la [ 31:2 ] ,sa [ 1:0 ] , and high byte enable shbe y for address decode. the esc decodes the following set of addresses. 1. bios memory space. 2. i/o addresses contained within the esc. 3. configuration registers. 4. x-bus peripherals. 5. memory addresses for accessing apic. 4.1 bios memory space the esc supports a total of 512 kbytes of bios. the esc will assert the lbioscs y signal for memory cycles decoded to be in the bios space. the 512 kbytes of bios includes the conventional 128 kbytes of bios and 384 kbytes of enlarged bios. the 128 kbytes conventional bios memory space is mapped at 1 mbyte boundary between memory address 000e0000h 000fffffh. the 128 kbyte conventional bios memory space is split into one 64 kbyte region, and four 16 kbyte regions. these regions are low bios region 1 (000e0000h 000e3fffh), low bios region 2 (000e4000h 000e7fffh), low bios region 3 (000e8000h 000ebfffh), and low bios region 4 (000ec000h 000effffh) and high bios region (000f0000h 000fffffh). the esc will assert the lbioscs y signal for memory cycles to these regions if the corresponding configuration bits in the bios chip select a register are set to enable (see table 3). the conventional bios is aliased at multiple memory regions. the aliased memory regions are at 16 mbyte boundary (high bios only), 4 gbyte minus 1 mbyte boundary, and 4 gbyte boundary. the esc will assert lbioscs y for memory cycles to these aliased regions if the corresponding configuration bits in the bios chip select b register are also set to enable (see table 3). the esc supported vga bios on the motherboard by aliasing the vga bios region to the conventional bios region. the vga bios is accessed at memory region 0000c0000h 0000c7fff. the vga bios region is divided into a low vga region (000c0000h 000c3fffh) and a high vga region (000c4000h 000c7fffh). if the bios chip select b register bit 0 (low vga bios enable) and bit 1 (high vga bios enable) are set to enable, memory accesses to low vga bios region and high vga bios region will be aliased to conventional low bios region 1 and low bios region 2 respectively and the esc will assert lbioscs y the esc supports the 384 kbytes of enlarged bios as specified by the pci specification. this 384 kbyte region is mapped in memory space below the 4 gbyte aliased conventional bios. the enlarged bios is accessed between fff80000h fffdffffh memory space. if the enlarged bios is enabled in the bios enable chip select 1 register bit 5 (enlarged bios enable), the esc will assert lbioscs y signal for access- es to this region. bios location auto-detection some applications require that flash-eprom based bios be updated in the system from the data coming from the floppy disk. to support this, the x-bus signals must be properly controlled (i.e. the esc's x-bus control logic must be aware of physical bios locationex-bus or isa bus). this is supported transparently to the software by configuring esc's x-bus logic during reset using the slowh y pin. 98
82374eb/82374SB logic level on slowh y pin is sampled at the end of reset sequence to determine whether bios resides on the x-bus (1) or on the isa bus (0). this information is used by the esc to control the x-bus transceivers during bios access. 290476 65 figure 2. bios memory map 99
82374eb/82374SB table 3. bios chip select enable table memory address range bios high en bios enl en bios vga low en bios high vga en bios 16m en lbioscs y asserted low bios en 1234 000c0000h to xxxxx x 0 xxno 000c3fffh xxxxx x 1 x x yes 000c4000h to xxxxx x x 0 xno 000c7fffh xxxxx x x 1 x yes 000e0000h to 0 xxxxxxxxno 000e3fffh 1 xxxxxxxxyes 000e4000h to x 0 xxxxxxxno 000e7fffh x 1 xxxxxxxyes 000e8000h to x x 0 xxxxxxno 000ebfffh x x 1 xxxxxxyes 000ec000h to x x x 0 xxxxxno 000effffh x x x 1 xxxxxyes 000f0000h to xxxx 0 xxxxno 000fffffh xxxx 1 xxxxyes (960kb to 1mb) 16mb) (16mb-64kb to 00ffffffh 00ff0000h to x x x x x x x x x x x x 1 0 x x x x x x xx x 1 0 0 yes no ffee0000h to 0 xxxxxxxxno ffee3fffh 1 xxxxxxxxyes ffee4000h to x 0 xxxxxxxno ffee7fffh x 1 xxxxxxxyes ffee8000h to x x 0 xxxxxxno ffeebfffh x x 1 xxxxxxyes ffeec000h to x x x 0 xxxxxno ffeeffffh x x x 1 xxxxxyes ffef0000h to xxxx 0 xxxxno ffefffffh xxxx 1 xxxxyes 4g 128kb (4gb 512kb to fffdffffh fff80000h to x x x x x x x x x x 1 0 x x x x x x yes no fffe0000h to 0 xxxxxxxxno fffe3fffh 1 xxxxxxxxyes fffe4000h to x 0 xxxxxxxno fffe7fffh x 1 xxxxxxxyes 100
82374eb/82374SB table 3. bios chip select enable table (continued) memory address range bios high en bios enl en bios vga low en bios high vga en bios 16m en lbioscs y asserted low bios en 1234 fffebfffh fffe8000h to x xx x 0 1 x xx x x x x x x x x x yes no fffeffffh fffec000h to x x x x x x 1 0 x x x x x x x x x x yes no ffffffffh ffff0000h to x x x x x x x x 1 0 x x x x x x x x yes no notes: 1. ``x'' in the above table represents a don't care condition. 2. all the region control bits for the bios space are in the bios chip select a register and bios chip select 2 register at configuration offsets 42h and 43h respectively. 4.2 i/o addresses contained within the esc the esc integrates functions like dma, programmable interrupt controller, and timers. all the compatibility registers associated with these functions are also integrated into the esc. the esc also integrates some additional registers like eisa system id register in order to reduce the overall chip count in the system. all the registers integrated in the esc are located in the i/o range. these are 8-bit registers and are accessed through the esc eisa interface. the esc internal registers are at fixed i/o locations with the exception of dma scatter-gather registers. the dma scatter-gather registers default to the i/o addresses 0410h to 043fh upon reset. these registers can be relocated by programming the scatter-gather relocate base address register. the dma scatter-gather registers can be relocated to i/o addresses range xx10h-xx3fh. registers at i/o addresses 70h, 372h, and 3f2h are shared registers between esc and external logic. port 70h is duplicated in the real time clock logic. bit 3 of ports 372h and 3f2h reside in the esc and the other bits reside in the floppy disk controller. table 4 documents the i/o address to the esc internal registers. table 4. esc i/o register address map address (hex) address (bit) type name block fedc ba98 7654 3210 0000h 0000 0000 000x 0000 r/w dma1 ch0 base and current address dma 0001h 0000 0000 000x 0001 r/w dma1 ch0 base and current count dma 0002h 0000 0000 000x 0010 r/w dma1 ch1 base and current address dma 0003h 0000 0000 000x 0011 r/w dma1 ch1 base and current count dma 0004h 0000 0000 000x 0100 r/w dma1 ch2 base and current address dma 101
82374eb/82374SB table 4. esc i/o register address map (continued) address (hex) address (bit) type name block fedc ba98 7654 3210 0005h 0000 0000 000x 0101 r/w dma1 ch2 base and current count dma 0006h 0000 0000 000x 0110 r/w dma1 ch3 base and current address dma 0007h 0000 0000 000x 0111 r/w dma1 ch3 base and current count dma 0008h 0000 0000 000x 1000 r/w dma1 status(r) command(w) register dma 0009h 0000 0000 000x 1001 wo dma1 write request dma 000ah 0000 0000 000x 1010 wo dma1 write single mask bit dma 000bh 0000 0000 000x 1011 wo dma1 write mode dma 000ch 0000 0000 000x 1100 wo dma1 clear byte pointer dma 000dh 0000 0000 000x 1101 wo dma1 master clear dma 000eh 0000 0000 000x 1110 wo dma1 clear mask dma 000fh 0000 0000 000x 1111 r/w dma1 read/write all mask register bits dma 0020h 0000 0000 001x xx00 r/w int 1 control pic 0021h 0000 0000 001x xx01 r/w int 1 mask pic 0022h 0000 0000 0010 0010 r/w configuration address index conf 0023h 0000 0000 0010 0011 r/w configuration data index conf 0040h 0000 0000 010x 0000 r/w timer 1 counter 0esystem clock tc 0041h 0000 0000 010x 0001 r/w timer1 counter 1erefresh request tc 0042h 0000 0000 010x 0010 r/w timer 1 counter 2espeaker tone tc 0043h 0000 0000 010x 0011 wo timer 1 command mode tc 0048h 0000 0000 010x 1000 r/w timer 2 counter 0efail-safe timer tc 0049h 0000 0000 010x 1001 r/w timer 2 counter 1ereserved tc 004ah 0000 0000 010x 1010 r/w timer 2 counter 2ecpu speed control tc 004bh 0000 0000 010x 1011 wo timer 2 command mode register tc 0061h 0000 0000 0110 00x1 r/w nmi status and control control 102
82374eb/82374SB table 4. esc i/o register address map (continued) address (hex) address (bit) type name block fedc ba98 7654 3210 0070h 1 0000 0000 0111 0xx0 wo nmi mask control 0080h 0000 0000 100x 0000 r/w dma page registerereserved dma 0081h 0000 0000 100x 0001 r/w dma channel 2 page dma 0082h 0000 0000 1000 0010 r/w dma channel 3 page dma 0083h 0000 0000 100x 0011 r/w dma channel 1 page dma 0084h 0000 0000 100x 0100 r/w dma page registerereserved dma 0085h 0000 0000 100x 0101 r/w dma page registerereserved dma 0086h 0000 0000 100x 0110 r/w dma page registerereserved dma 0087h 0000 0000 100x 0111 r/w dma channel 0 page dma 0088h 0000 0000 100x 1000 r/w dma page registerereserved dma 0089h 0000 0000 100x 1001 r/w dma channel 6 page dma 008ah 0000 0000 100x 1010 r/w dma channel 7 page dma 008bh 0000 0000 100x 1011 r/w dma channel 5 page dma 008ch 0000 0000 100x 1100 r/w dma page registerereserved dma 008dh 0000 0000 100x 1101 r/w dma page registerereserved dma 008eh 0000 0000 100x 1110 r/w dma page registerereserved dma 008fh 0000 0000 100x 1111 r/w dma refresh page dma 0092h 0000 0000 1001 0010 r/w system control port control 00a0h 0000 0000 101x xx00 r/w int 2 control pic 00a1h 0000 0000 101x xx01 r/w int 2 mask pic 00b2h 0000 0000 1011 0010 r/w advanced power management control apm 00b3h 0000 0000 1011 0011 r/w advanced power management status apm 00c0h 0000 0000 1100 000x r/w dma2 ch0 base and current address dma 00c2h 0000 0000 1100 001x r/w dma2 ch0 base and current count dma 00c4h 0000 0000 1100 010x r/w dma2 ch1 base and current address dma 00c6h 0000 0000 1100 011x r/w dma2 ch1 base and current count dma 103
82374eb/82374SB table 4. esc i/o register address map (continued) address (hex) address (bit) type name block fedc ba98 7654 3210 00c8h 0000 0000 1100 100x r/w dma2 ch2 base and current address dma 00cah 0000 0000 1100 101x r/w dma2 ch2 base and current count dma 00cch 0000 0000 1100 110x r/w dma2 ch3 base and current address dma 00ceh 0000 0000 1100 111x r/w dma2 ch3 base and current count dma 00d0h 0000 0000 1101 000x r/w dma2 status(r) command(w) register dma 00d2h 0000 0000 1101 001x wo dma2 write request dma 00d4h 0000 0000 1101 010x wo dma2 write single mask bit dma 00d6h 0000 0000 1101 011x wo dma2 write mode dma 00d8h 0000 0000 1101 100x wo dma2 clear byte pointer dma 00dah 0000 0000 1101 101x wo dma2 master clear dma 00dch 0000 0000 1101 110x wo dma2 clear mask dma 00deh 0000 0000 1101 111x r/w dma2 read/write all mask register bits dma 00f0h 0000 0000 1111 0000 wo reset irq13 irq13 0372h 2 0000 0011 0111 0010 wo secondary floppy disk digital output fdccs y 03f2h 2 0000 0011 1111 0001 wo primary floppy disk digital output fdccs y 0400h 0000 0100 0000 0000 r/w reserved dma 0401h 0000 0100 0000 0001 r/w dma1 ch0 base/current count dma 0402h 0000 0100 0000 0010 r/w reserved dma 0403h 0000 0100 0000 0011 r/w dma1 ch1 base/current count dma 0404h 0000 0100 0000 0100 r/w reserved dma 0405h 0000 0100 0000 0101 r/w dma1 ch2 base/current count dma 0406h 0000 0100 0000 0110 r/w reserved dma 0407h 0000 0100 0000 0111 r/w dma1 ch3 base/current count dma 0408h 0000 0100 0000 1000 r/w reserved dma 104
82374eb/82374SB table 4. esc i/o register address map (continued) address (hex) address (bit) type name block fedc ba98 7654 3210 0409h 0000 0100 0000 1001 r/w reserved dma 040ah 0000 0100 0000 1010 r/w dma chaining mode status/interrupt pending dma 040bh 0000 0100 0000 1011 wo dma1 extended mode dma 040ch 0000 0100 0000 1100 wo chaining buffer control dma 040dh 0000 0100 0000 1101 r/w reserved dma 040eh 0000 0100 0000 1110 r/w reserved dma 040fh 0000 0100 0000 1111 r/w reserved dma 0410h 0000 0100 0010 0000 wo dma ch0 s-g command dma 0411h 0000 0100 0010 0001 wo dma ch1 s-g command dma 0412h 0000 0100 0010 0010 wo dma ch2 s-g command dma 0413h 0000 0100 0010 0011 wo dma ch3 s-g command dma 0415h 0000 0100 0010 0101 wo dma ch5 s-g command dma 0416h 0000 0100 0010 0110 wo dma ch6 s-g command dma 0417h 0000 0100 0010 0111 wo dma ch7 s-g command dma 0418h 0000 0100 0010 1000 wo dma ch0 s-g status dma 0419h 0000 0100 0010 1001 wo dma ch1 s-g status dma 041ah 0000 0100 0010 1010 wo dma ch2 s-g status dma 041bh 0000 0100 0010 1011 wo dma ch3 s-g status dma 041dh 0000 0100 0010 1101 wo dma ch5 s-g status dma 041eh 0000 0100 0010 1110 wo dma ch6 s-g status dma 041fh 0000 0100 0010 1111 wo dma ch7 s-g status dma 0420h 0000 0100 0010 0000 ro dma ch0 s-g descriptor pointer dma 0421h 0000 0100 0010 0001 ro dma ch0 s-g descriptor pointer dma 0422h 0000 0100 0010 0010 ro dma ch0 s-g descriptor pointer dma 0423h 0000 0100 0010 0011 ro dma ch0 s-g descriptor pointer dma 0424h 0000 0100 0010 0100 ro dma ch1 s-g descriptor pointer dma 105
82374eb/82374SB table 4. esc i/o register address map (continued) address (hex) address (bit) type name block fedc ba98 7654 3210 0425h 0000 0100 0010 0101 ro dma ch1 s-g descriptor pointer dma 0426h 0000 0100 0010 0110 ro dma ch1 s-g descriptor pointer dma 0427h 0000 0100 0010 0111 ro dma ch1 s-g descriptor pointer dma 0428h 0000 0100 0010 1000 ro dma ch2 s-g descriptor pointer dma 0429h 0000 0100 0010 1001 ro dma ch2 s-g descriptor pointer dma 042ah 0000 0100 0010 1010 ro dma ch2 s-g descriptor pointer dma 042bh 0000 0100 0010 1011 ro dma ch2 s-g descriptor pointer dma 042ch 0000 0100 0010 1100 ro dma ch3 s-g descriptor pointer dma 042dh 0000 0100 0010 1101 ro dma ch3 s-g descriptor pointer dma 042eh 0000 0100 0010 1110 ro dma ch3 s-g descriptor pointer dma 042fh 0000 0100 0010 1111 ro dma ch3 s-g descriptor pointer dma 0434h 0000 0100 0011 0100 ro dma ch5 s-g descriptor pointer dma 0435h 0000 0100 0011 0101 ro dma ch5 s-g descriptor pointer dma 0436h 0000 0100 0011 0110 ro dma ch5 s-g descriptor pointer dma 0437h 0000 0100 0011 0111 ro dma ch5 s-g descriptor pointer dma 0438h 0000 0100 0011 1000 ro dma ch6 s-g descriptor pointer dma 0439h 0000 0100 0011 1001 ro dma ch6 s-g descriptor pointer dma 043ah 0000 0100 0011 1010 ro dma ch6 s-g descriptor pointer dma 043bh 0000 0100 0011 1011 ro dma ch6 s-g descriptor pointer dma 106
82374eb/82374SB table 4. esc i/o register address map (continued) address (hex) address (bit) type name block fedc ba98 7654 3210 043ch 0000 0100 0011 1100 ro dma ch7 s-g descriptor pointer dma 043dh 0000 0100 0011 1101 ro dma ch7 s-g descriptor pointer dma 043eh 0000 0100 0011 1110 ro dma ch7 s-g descriptor pointer dma 043fh 0000 0100 0011 1111 ro dma ch7 s-g descriptor pointer dma 0461h 0000 0100 0110 0001 r/w extended nmi and reset control control 0462h 0000 0100 0110 0010 r/w nmi i/o interrupt port control 0464h 0000 0100 0110 0100 ro last eisa bus master granted (l) control 0480h 0000 0100 1000 0000 r/w reserved dma 0481h 0000 0100 1000 0001 r/w dma ch2 high page dma 0482h 0000 0100 1000 0010 r/w dma ch3 high page dma 0483h 0000 0100 1000 0011 r/w dma ch1 high page dma 0484h 0000 0100 1000 0100 r/w reserved dma 0485h 0000 0100 1000 0101 r/w reserved dma 0486h 0000 0100 1000 0110 r/w reserved dma 0487h 0000 0100 1000 0111 r/w dma ch0 high page dma 0488h 0000 0100 1000 1000 r/w reserved dma 0489h 0000 0100 1000 1001 r/w dma ch6 high page dma 048ah 0000 0100 1000 1010 r/w dma ch7 high page dma 048bh 0000 0100 1000 1011 r/w dma ch5 high page dma 048ch 0000 0100 1000 1110 r/w reserved dma 048dh 0000 0100 1000 1101 r/w reserved dma 048eh 0000 0100 1000 1110 r/w reserved dma 048fh 0000 0100 100x 1111 r/w dma refresh high page dma 04c2h 0000 0100 1100 0010 r/w reserved dma 107
82374eb/82374SB table 4. esc i/o register address map (continued) address (hex) address (bit) type name block fedc ba98 7654 3210 04c6h 0000 0100 1100 0110 r/w dma ch5 high base & current count dma 04cah 0000 0100 1100 1010 r/w dma ch6 high base & current count dma 04ceh 0000 0100 1100 1110 r/w dma ch7 high base & current count dma 04d0h 0000 0100 1101 0000 r/w int-1 edge/level control pic 04d1h 0000 0100 1101 0001 r/w int-2 edge/level control pic 04d2h 0000 0100 1101 0010 r/w reserved dma 04d3h 0000 0100 1101 0011 r/w reserved dma 04d4h 0000 0100 1101 0100 r/w dma2 chaining mode dma 04d5h 0000 0100 1101 1001 r/w reserved dma 04d6h 0000 0100 1101 0010 wo dma2 extended mode dma 04d7h 0000 0100 1101 0111 r/w reserved dma 04d8h 0000 0100 1101 1000 r/w reserved dma 04d9h 0000 0100 1101 1001 r/w reserved dma 04dah 0000 0100 1101 1010 r/w reserved dma 04dbh 0000 0100 1101 1011 r/w reserved dma 04dch 0000 0100 1101 1100 r/w reserved dma 04ddh 0000 0100 1101 1101 r/w reserved dma 04deh 0000 0100 1101 1110 r/w reserved dma 04dfh 0000 0100 1101 1111 r/w reserved dma 04e0h 0000 0100 1110 0000 r/w dma ch0 stop register bits [ 7:2 ] dma 04e1h 0000 0100 1110 0001 r/w dma ch0 stop register bits [ 15:8 ] dma 04e2h 0000 0100 1110 0010 r/w dma ch0 stop register bits [ 23:16 ] dma 04e3h 0000 0100 1110 0011 r/w reserved dna 04e4h 0000 0100 1110 0100 r/w dma ch1 stop register bits [ 7:2 ] dma 04e5h 0000 0100 1110 0101 r/w dma ch1 stop register bits [ 15:8 ] dma 108
82374eb/82374SB table 4. esc i/o register address map (continued) address (hex) address (bit) type name block fedc ba98 7654 3210 04e6h 0000 0100 1110 0110 r/w dma ch1 stop register bits [ 23:16 ] dma 04e7h 0000 0100 1110 0111 r/w reserved dma 04e8h 0000 0100 1110 1000 r/w dma ch2 stop register bits [ 7:2 ] dma 04e9h 0000 0100 1110 1001 r/w dma ch2 stop register bits [ 15:8 ] dma 04eah 0000 0100 1110 1010 r/w dma ch2 stop register bits [ 23:16 ] dma 04ebh 0000 0100 1110 1011 r/w reserved dma 04ec 0000 0100 1110 1100 r/w dma ch3 stop register bits [ 7:2 ] dma 04edh 0000 0100 1110 1101 r/w dma ch3 stop register bits [ 15:8 ] dma 04eeh 0000 0100 1110 1110 r/w dma ch3 stop register bits [ 23:16 ] dma 04efh 0000 0100 1110 1111 r/w reserved dma 04f0h 0000 0100 1111 0000 r/w reserved dma 04f1h 0000 0100 1111 0001 r/w reserved dma 04f2h 0000 0100 1111 0010 r/w reserved dma 04f3h 0000 0100 1111 0011 r/w reserved dma 04f4h 0000 0100 1111 0100 r/w dma ch5 stop register bits [ 7:2 ] dma 04f5h 0000 0100 1111 0101 r/w dma ch5 stop register bits [ 15:8 ] dma 04f6h 0000 0100 1111 0110 r/w dma ch5 stop register bits [ 23:16 ] dma 04f7h 0000 0100 1111 0111 r/w reserved dma 04f8h 0000 0100 1111 1000 r/w dma ch6 stop register bits [ 7:2 ] dma 04f9h 0000 0100 1111 1001 r/w dma ch6 stop register bits [ 15:8 ] dma 04fah 0000 0100 1111 1010 r/w dma ch6 stop register bits [ 23:16 ] dma 109
82374eb/82374SB table 4. esc i/o register address map (continued) address (hex) address (bit) type name block fedc ba98 7654 3210 04fbh 0000 0100 1111 1011 r/w reserved dma 04fc 0000 0100 1111 1100 r/w dma ch7 stop register bits [ 7:2 ] dma 04fdh 0000 0100 1111 1101 r/w dma ch7 stop register bits [ 15:8 ] dma 04feh 0000 0100 1111 0111 r/w dma ch7 stop register bits [ 23:16 ] dma 04ffh 0000 0100 1111 1111 r/w reserved dma 0c00h 0000 1100 0000 0000 r/w configuration ram page register conf 0c80h 0000 1100 100 0000 ro system board id byte lane 1 bits [ 7:0 ] board id 0c81h 0000 1100 100 0001 ro system board id byte lane 2 bits [ 15:8 ] board id 0c82h 0000 1100 100 0010 ro system board id byte lane 3 bits [ 23:16 ] board id 0c83h 0000 1100 1000 0011 ro system board id byte lane 4 bits [ 31:24 ] board id notes: 1. port 70h resides in the esc in addition the lower 7 bits of port 70h reside in real time clock also. 2. bit 3 of ports 372h and 3f2h reside in the esc while the other bits reside on the isa bus. 4.3 configuration addresses esc configuration registers are accessed through i/o registers 22h and 23h. these i/o registers are used as index address register (22h) and index data register (23h). the index address register is used to write the configuration register address. the data (configuration register address) in register 22h is used to decode a configuration register. the selected configuration register can be read or written to by performing a read or a write operation to the index data register at i/o address 23h. table 5. configuration register index address configuration abbreviation register name offset 00 01h e reserved 02h escid esc id 03 07h e reserved 08h rid revision id 09 3fh e reserved 110
82374eb/82374SB table 5. configuration register index address (continued) configuration abbreviation register name offset 40h ms mode select 41h e reserved 42h bioscsa bios chip select a 43h bioscsb bios chip select b 44 4ch e reserved 4dh clkdiv bclk clock divisor 4eh pcsa peripheral chip select a 4fh pcsb peripheral chip select b 50h eisaid1 eisa id byte 1 51h eisaid2 eisa id byte 2 52h eisaid3 eisa id byte 3 53h eisaid4 eisa id byte 4 54 56h e reserved 57h sgrba scatter-gather relocate base address 58h e reserved 59h apicba apic base address relocation 60h pirqrc0 pirq0 y route control 61h pirqrc1 pirq1 y route control 62h pirqrc2 pirq2 y route control 63h pirqrc3 pirq3 y route control 64h gpcsla0 general purpose chip select 0 base low address 65h gpcsha0 general purpose chip select 0 base high address 66h gpcsm0 general purpose chip select 0 mask 67h e reserved 68h gpcsla1 general purpose chip select 1 base low address 69h gpcsha1 general purpose chip select 1 base high address 6ah gpcsm1 general purpose chip select 1 mask 6bh e reserved 6ch gpcsla2 general purpose chip select 2 base low address 6dh gpcsha2 general purpose chip select 2 base high address 111
82374eb/82374SB table 5. configuration register index address (continued) configuration abbreviation register name offset 6eh gpcsm2 general purpose chip select 2 mask 6fh gpxbc general purpose peripheral x-bus control 70h pacc pic/apic configuration control 71 87h e reserved 88h tstc test control 89 9fh e reserved a0h smicntl smi control a2-a3h smien smi enable a4-a7h see system event enable a8h ftmr fast off timer a9h e reserved aa-abh smireq smi request ach ctltmrl clock scaling stpclk y low timer adh e reserved aeh ctltmrh clock scaling stpclk y high timer af-ffh e reserved 4.4 x-bus peripherals the esc generates chip selects for certain functions that typically reside on the x-bus. the esc asserts the chip selects combinatorially from the la addresses. the esc generates chip select signals for the keyboard controller, floppy disk controller, ide, parallel port, serial port, and general purpose peripherals. the esc also generates read and write strobes for real time clock and configuration ram. the read and write strobes are a function of la addresses, the isa read and write strobes (iorc y and iowc y ), and bclk. all of the peripherals supported by the esc are at fixed i/o addresses with the exception of the general purpose peripherals. the esc support for these peripherals can be enabled or disabled through configuration registers peripheral chip select a and peripheral chip select b. the general purpose peripherals are mapped to i/o addresses by programming a set of configuration registers: general purpose chip select x base low address register, general purpose chip select x base high address register, and general purpose chip select x mask register. 112
82374eb/82374SB table 6. x-bus chip selects decode address (hex) address (bit) r/w name chip select fedc ba98 7654 3210 0060h 0000 0000 0110 00x0 r/w keyboard controller kybdcs y 0064h 0000 0000 0110 01x0 r/w controller keyboard kybdcs y 0070h 0000 0000 0111 0xx0 w clock real time rtcale 0071h 0000 0000 0111 0xx1 r/w clock real time rtcrd y rtcwr y / 0177h 0170h 0000 0001 0111 0xxx r/w 0-secondary ide controller (idecs0 y ) ecs [ 2:0 ] e 011 01f7h 01f0h 0000 0001 1111 0xxx r/w 0-primary ide controller (idecs0 y ) ecs [ 2:0 ] e 011 027bh 0278h 0000 0010 0111 1011 1000 to r/w lpt3 parallel port (lptcs y ) ecs [ 2:0 ] e 010 02f8h 02ffh 0000 0010 1111 xxxx r/w com2 serial port (comxcs y ) ecs [ 2:0 ] e 00x 0375h 0370h 0000 0011 0111 0101 0000 to r/w secondary controller- floppy disk fdccs y 0376h 0000 0011 0111 0111 r/w 1 secondary ide controller (idecs1 y ) ecs [ 2:0 ] e 100 0377h 0000 0011 0111 0110 r/w 1 secondary ide controller (idecs1 y ) ecs [ 2:0 ] e 100 0377h 0000 0011 0111 0111 r/w secondary controller- floppy disk fdccs y 037bh 0378h 0000 0011 0111 1011 1000 to r/w lpt2 parallel port (lptcs y ) ecs [ 2:0 ] e 010 03bfh 03bch 0000 0011 1011 11xx r/w lpt 1 parallel port (lptcs y ) ecs [ 2:0 ] e 010 0375h 03f0h 0000 0011 1111 0101 0000 to r/w primary controller- floppy disk fdccs y 03f6h 0000 0011 0111 0110 r/w 1-primary ide controller (idecs1 y ) ecs [ 2:0 ] e 100 113
82374eb/82374SB table 6. x-bus chip selects decode (continued) address (hex) address (bit) r/w name chip select fedc ba98 7654 3210 03f7h 0000 0011 0111 0111 r/w ide controller 1-primary (idecs1 y ) ecs [ 2:0 ] e 100 03f7h 0000 0011 0111 0111 r/w primary controller- floppy disk fdccs y 03ffh 03f8h 0000 0011 1111 1000 r/w com 1 serial port (comxcs y ) ecs [ 2:0 ] e 00x 08ffh 0800h 0000 1000 xxxx xxxx w/r ram configuration cramrd y cramwr y / 4.5 i/o apic registers the apic's registers are indirectly address through two 32 bit registers located in the cpu's memory spacee the i/o register select (ioregsel) and i/o window (iowin) registers (table 7). these registers can be relocated via the apic base address relocation register and are aligned on 128 bit boundaries. to access an i/o apic register, the ioregsel register is written with the address of the intended apic register. bits [ 7:0 ] of the ioregsel register provide the address offset (table 8). the iowin register then becomes a 32-bit window pointing to the register selected by the ioregsel register. note that, for each redirection table register, there are two offset addresses (e.g., address offset 10h selects ioredtbl0 bits [ 31:0 ] and 11h selects ioredtbl0 bits [ 63:32 ] . table 7. memory address for accessing apic registers memory mnemonic register name access address fec0 x000h ioregsel i/o register select r/w (82374eb) fec0 xy00h (82374SB) fec0 x010h iowin i/o window r/w (82374eb) fec0 xy10h (82374SB) note: xy are determined by the x and y (82374SB only) fields in the apic base address relocation register. range for x e 0-fh and the range for y e 0,4,8,ch. 114
82374eb/82374SB table 8. i/o apic registers memory mnemonic register name access address 00h ioapicid i/o apic id r/w 01h ioapicver i/o apic version ro 02h ioapicarb i/o apic arbitration id ro 10-2fh ioredtbl [ 0:15 ] redirection table (entries 0-15) (63 bits each) r/w note: address offset is determined by i/o register select bits [ 7:0 ] 5.0 eisa controller functional description 5.1 overview the eisa controller in the esc provides master/slave eisa interface function for the esc internal resources. in addition, the esc acts as an eisa central resource for the system. as a system central resource, the eisa controller is responsible for generating the translation control signals necessary for bus-to-bus transfers. these translation includes transfer between devices on eisa bus and isa bus and transfers between different size master device and slave device. the eisa controller generates the control signals for eisa data swap buffers integrated in the pceb. the esc eisa interface generates cycles for dma transfers, and refresh. the esc internal registers are accessed through the eisa slave interface. the esc is responsible for supporting the following: service eisa master cycles to: # eisa slaves devices. # isa slave devices. # esc internal registers. service isa master cycles to: # eisa slave devices. # isa (mis-matched) slave devices. # esc internal registers. service dma cycles : # from/to dma slave on the eisa bus to/from memory on the eisa/isa bus. # from/to dma slave on the isa bus to/from memory on the eisa/isa bus. # from/to dma slave on the eisa/isa bus to/from memory on the pci bus. service refresh cycles the eisa controller will service the refresh cycle by generating the appropriate address and command signals. these cycles are initiated by either the esc internal refresh logic or by an external isa-bus master. 115
82374eb/82374SB generates data swap buffer control the eisa controller generates the control signals for the data bus swap control (assembly/disassembly) and swapping process to support data size mismatches of the devices on the eisa and isa buses. the actual data steering and swapping is performed by the pceb. generate wait states the wait state generator is responsible for generating the wait states based on the sampling of the exrdy, chrdy, nows y and the default wait states. the default wait state depends on the cycle type. 5.2 clock generation the esc is generates the eisa bus clock. the esc uses a divider circuit to generate the eisa bus clock. the esc supports pci bus frequencies between 25 mhz and 33 mhz. the pci clock is divided by 3 or 4 by the clock generation logic in the esc. the eisa clock divisor register bits [ 2:0 ] select the divide value. the esc provides the eisa bus clock as the bclkout output. although the esc is capable of driving 240 pf load on the bclkout pin, it is recommended that this signal be buffered to protect the eisa bclk signal. the esc eisa control logic and eisa interface is synchronous to the bclk input. a maximum delay of 15 ns is allowed between the bclkout output and the bclk input for proper device functionality. table 9. pciclk and bclk frequency relationship pciclk divisor bclk (mhz) (programmable) (mhz) 25 3 8.33 30 4 * 7.5 33.3 4 * 8.33 note: the esc wakes up after reset with a default divisor value of 4. 5.2.1 clock stretching the esc is capable of stretching eisa bus clock (bclkout) for pceb generated eisa cycles. the esc stretches the eisa bus clock (bclkout) in order to minimize the synchronization penalty between pci clock and eisa clock for accesses to eisa bus by pci agents. the pceb initiates an eisa cycle by asserting start y synchronous to pciclk. the esc ensures the start y minimum pulse width is met by stretching the eisa bus clock low time. the esc samples start y on every pciclk when the pceb has the eisa bus. after sampling start y asserted, the esc delays the rising edge of bclkout until the start y has met the 115 ns minimum pulse width specification. 116
82374eb/82374SB 290476 66 figure 3. bclk stretching 5.3 eisa master cycles eisa master cycles are initiated on the eisa bus by an eisa master (including pceb for pci agents). these cycles are accesses to the following resources: # eisa slaves devices (including pceb for pci agents) # isa slave devices # esc internal registers (8-bit eisa slave) an eisa master gains control of the bus by asserting mreqx y (pereq y in case of pceb) to the esc. the esc, after performing the necessary arbitration, asserts the corresponding mackn y (negates eisahold in case of the pceb). refer to section 7.0 for arbitration protocol. in response to receiving the acknowledge signal, the eisa master starts the cycle by driving the bus with la [ 31:02 ] ,be [ 3:0 ] , w/r, and m/io. the eisa master then asserts start y to indicate the beginning of the current cycle. a 16-bit eisa master will also assert master16 y at this time. the esc generates sbeh y , s1, and s0 signals from the be [ 3:0 ] y signals. 5.3.1 eisa master to 32-bit eisa slave an eisa slave after decoding it's address asserts ex32 y or ex16 y . the eisa master and the esc use these signals to determine the eisa slave data size. the 32-bit or 16-bit eisa master continues with the cycles if ex32 y or ex16 y is asserted respectively. the esc acts as a central resources for the eisa master and generates cmd y for the cycles. the esc asserts cmd y on the same bclk edge that start y is negated. the esc monitors the exrdy signal on the eisa bus to determine when to negate the cmd y . an eisa slave can extend the cycle by negating exrdy. eisa specification require that exrdy not be held negated for more than 2.5 m s. a burstable eisa slave asserts slburst y signal the same time the slave decodes it's address. the eisa master will sample slburst y and assert msburst y if it is capable of bursting. the esc keeps the cmd y asserted during a burst eisa transfer. the esc deasserts cmd y to indicate the end of the burst transfer after the eisa master deasserts msburst y . 117
82374eb/82374SB if ex16 y is asserted, a 32-bit eisa master backs-off the bus by floating be [ 3:0 ] y and start y (see section 5.3.4). the esc acts as a central resource for the eisa master in this case and takes over the mastership of the eisa bus by deriving start y , cmd y , and the appropriate byte enables. the esc generates the neces- sary translation cycles for the eisa master and returns the bus ownership to the master by asserting ex32 y and ex16 y . the esc monitors the exrdy signal on the eisa bus to determine when to negate the cmd y . an eisa slave can extend the cycle by negating exrdy. eisa specification require that exrdy not be held negated for more than 2.5 m s. a burstable eisa slave will assert the slburst y signal the same time when its address is decoded. the eisa master will sample slburst y and assert msburst y if it is capable of bursting. the esc keeps the cmd y asserted during a burst eisa transfer. the esc deasserts cmd y to indicate the end of the burst transfer after the eisa master deasserts msburst y . 290476 67 figure 4. standard eisa master to eisa slave cycle 118
82374eb/82374SB 290476 68 figure 5. burst eisa master to eisa slave cycle 5.3.2 eisa master to 16-bit isa slave an isa slave, after decoding it's address, asserts m16 y or io16 y . the esc monitors the ex32 y , ex16 y , m16 y , and io16 y signals to determine the slave type. if ex32 y and ex16 y are negated and m16 y or io16 y is asserted, the esc performs isa translation cycles for the eisa bus master by generating bale, mrdc y , mwrc y , iorc y , iowc y signals as appropriate. the isa slave can add wait states by negating chrdy. the esc samples chrdy and translate it into exrdy. 5.3.3 eisa master to 8-bit eisa/isa slaves an 8-bit slave does not positively acknowledge it's selection by asserting any signal. the absence of an asserted ex32 y , ex16 y , m16 y , and io16 y indicate to the esc that an 8-bit device has been selected. the eisa master is backed-off the bus, and the esc takes over mastership of the eisa/isa bus. the esc will run 8-bit translation cycles on the bus by deriving the eisa control signals and the isa control signals. a slave can extend the cycles by negating exrdy or chrdy signals. the esc (internal registers) is accessed as an 8-bit slave. 119
82374eb/82374SB 5.3.4 eisa master back-off during eisa master transfer where the master and slave size is mis-matched, the eisa master is required to back-off the bus on the first falling edge of bclk after start y is negated. the eisa master floats its start y ,be [ 3:0 ] y , and data lines at this time. this allows the esc to performs translation cycle. the master must back-off the bus if a master/slave data size mis-match is determined, regardless if data size translation is performed. at the end of the data size translation or transfer cycle control is transferred back to the bus master by the esc by driving ex32 y and ex16 y active on the falling edge of bclk, before the rising edge of bclk that the last cmd y is negated. an additional bclk is added at the end of the transfer to allow the exchanging of cycle control to occur. 290476 69 figure 6. eisa master back off cycle 120
82374eb/82374SB 5.4 isa master cycles isa cycles are initiated on the isa bus by an isa master. these cycles are accesses to the following system resources: # eisa slaves devices (including pceb for pci agents). # isa slave devices. # esc internal registers (8-bit eisa slave). the isa master initiates such a cycle by asserting the dreqx y line to the esc. the esc, after performing the necessary arbitration, asserts the corresponding dackx y line. upon receiving an acknowledge from the esc, the isa master asserts the master16 y signal line to indicate that it has control of the isa bus and a cycle on the isa bus will take place. the esc translates the isa address signals sbhe y , sa1, and sa0 to eisa byte enables be [ 3:0 ] y . 5.4.1 isa master to 32-/16-bit eisa slave an eisa slave will decode the address to determine if it has been selected. in response to a positive decode, the eisa slave will assert ex32 y or ex16 y . the esc samples these signals to determine if an eisa slave has been selected. if these signals are asserted, the esc will perform isa to eisa cycle translation by driving the eisa control signals. the isa master asserts one of the isa command signals mrdc y , mwtc y , iorc y or iowc y depending on whether or not the access is to a memory, an i/o device or an i/o register. the isa command signals will remain active until the end of the cycle. the esc will generate the eisa translation by generating the eisa control signals; start y , cmd y , m/io y , and w/r y . the eisa slave can add wait states by negating exrdy. the esc samples exrdy and translates it into chrdy. the esc will also generate the control signals to steer the data to the appropriate byte lanes for mis- matched cycles. 5.4.2 isa master to 16-bit isa slave an isa master initiates cycles to isa slave devices. these cycles are either memory read/write or i/o read/ write. the isa bus master is assumed to be 16-bit device, and it can access either 8- or 16-bit slave devices that reside on the isa bus. a 16-bit isa slave device will respond to a valid address by asserting m16 y for memory cycles and io16 y for i/o cycles. the esc is inactive during isa master cycles where either m16 y or io16 y is sampled asserted. 121
82374eb/82374SB 290476 71 figure 7. isa master to 16-bit isa slave cycles (3 bclks) 122
82374eb/82374SB 290476 70 figure 8. isa master to 16-bit isa slave extended cycle (4 bclks) 5.4.3 isa master to 8-bit eisa/isa slave an 8-bit slave does not positively acknowledge it's selection by asserting any signal. the absence of an asserted ex32 y , ex16 y , m16 y , and io16 y indicate to the esc that an 8-bit device has been selected. the eisa master is backed-off the bus, and the esc takes over mastership of the eisa/isa bus. the esc will run 8-bit translation cycles on the bus by deriving the eisa control signals and the isa control signals. a slave can extend the cycles by negating exrdy or chrdy signals. the esc (internal registers) is accessed as an 8-bit slave. 5.4.4 isa wait state generation there are three sources that can affect the generation of wait states for isa cycles. the first is the default wait states, which determines the standard or default isa bus cycle in the absence of any response from the slave. the second is cycle extension, which is indicated by the slave pulling the chrdy signal line inactive (low). the chrdy is high by default due to a pull-up resistor. thus, the cycle will be extended until the chrdy is returned to its active high value. the third way to change the number of wait states is when the slave asserts the nows y signal which makes the cycle shorter than the default or standard cycle. isa memory slaves (8- and 16-bits) and isa i/o slaves (only 8-bits) can shorten their default cycles by asserting the nows y signal lines. a 16-bit i/o slave cannot shorten its default cycles. when nows y is asserted at the same time the chrdy is negated by the isa slave device, nows y will be ignored and wait states will be added. (i.e.; chrdy has precedence over nows y .) dma devices (i/o) cannot add wait states, but memory can. table 10 shows the number of bclks for each cycle type (memory, i/o, dma), default, wait states added and with nows y asserted. 123
82374eb/82374SB table 10. number of bclks for isa master cycles cycle type bus no wait state standard chrdy e 1 one wait state size nows y e 0 nows y e 1 chrdy e 0 number of bclks read/write memory 16 2 3 4 read/write memory 8 4, 5 6 7 i/o read/write 16 3 3 4 i/o read/write 8 4, 5 6 7 dma compatible 8/16 8 8 10 dma type a (1) 8/16 na 6 7 dma type b (1) 8/16 na 4 5 dma type c (2) 8/16 na 2 3 notes: 1. if isa memory responds, the esc will extend the cycle by 1 bclk. 2. if isa memory responds, the esc will use dma type b read cycle timing. 5.5 mis-match cycles data size translation is performed by the esc for all mis-matched cycles. a mis-matched cycle is defined as a cycle in which the bus master and bus slave do not have equal data bus sizes (e.g., a 32-bit eisa master accessing a 16-bit isa slave). the data size translation is performed in conjunction with the pceb. the esc generates the appropriate cycles and data steering control signals for mis-matched cycles. the pceb uses the data steering control signals from the esc to latch and redirect the data to the appropriate byte lanes. the esc will perform one or more of the following operations depending on the master and slave type, transfer direction, and the number of byte enables active. table 11. mis-match master slave combinations master type cycle type slave type 32-bit 16-bit 16-bit 8-bit eisa eisa isa eisa/isa downshift 32-bit eisa with 16-bit burst standard match match match mis-match na mis-match na mis-match 32-bit eisa burst standard match match na mis-match na mis-match na mis-match 16-bit eisa burst standard mis-match mis-match match match na mis-match na mis-match note: na: not applicable. the cycle will never occur. 124
82374eb/82374SB 5.6 data swap buffer control logic for all mis-matched cycles, the esc is responsible for performing data size translations. the esc performs these data size translations by either becoming the master of the eisa/isa bus (see section 5.3.4) or by directing the flow of data to the appropriate byte lanes. in both cases, the esc generates data swap buffer control signals to perform data size translation. # sdcpyen [ 13,3:1 ] # sdcpyup # sdoe [ 2:0 ] y # sdle [ 3:0 ] y the data swap buffers are integrated in the pceb (see pceb data sheet section 8.0 for data swap buffer function description). the data size translation cycles consist of one or combinations of assembly, disassem- bly, copy up/down, and redrive. assembly this occurs during reads when an eisa master data size is greater than the slave data size. isa masters are required to perform assemble when accessing 8-bit slaves. assembly consists of two, three, or four cycles depending on the master data size, slave data size, and number of active byte enables. during the assembly process, the data is latched in to the pceb data latch/buffers. this data is driven or redriven on to the eisa bus during the last cycle. the master after initiating the cycle backs-off the bus (see the eisa master back-off section for details) when a mis-matched is detected. the esc becomes the bus master and runs the appropri- ate number of cycles. at the end of the last cycle, the esc transfer the control of bus back to the original master. disassembly this occurs during writes when the eisa master data size is greater than the slave data size. isa masters are required to perform disassemble when accessing 8-bit slaves. disassembly consists of two, three, or four cycles depending on the master data size, slave data size, and number of active byte enables. during the disassembly process, the data is latched in the pceb latch/buffers on the first cycle. this data is driven or redriven on to the eisa bus on subsequent cycles. the master after initiating the cycle backs-off the bus (see the eisa master back-off section for details) when a mis-matched is detected. the esc becomes the bus master and runs the appropriate number of cycles. at the end of the last cycle, the esc transfer the control of bus back to the original master. copy-up this occurs during reads when the master data size is greater than the slave data size and during writes when the master data size is smaller than the slave data size. the copy-up function is used for cycles with and without assembly/disassembly. copy-down this occurs during writes when the master data size is greater than the slave data size and during reads when the master data size is smaller than the slave data size. the copy-down function is used for cycles with and without assembly/disassembly. 125
82374eb/82374SB re-drive this occurs during reads and writes when both the master and slave are on the eisa/isa bus and the pceb is neither a master nor a slave. the re-drive function is always performed in conjunction with assembly/disas- sembly. during the assembly process, the last cycle is a re-drive cycle. during disassembly, all the cycles except the first cycle are re-drive cycles. 5.7 servicing dma cycles the esc is responsible for performing dma transfers. if the memory is determined (ex32 y or ex16 y assert- ed) to be on the eisa bus, the dma cycle can be ``a'', ``b'', or ``c'' type. if the memory is determined to be on the isa bus, then the dma cycle will run as a compatible cycle. the dma transfers are described in detail in section 8.0. 5.8 refresh cycles the esc support refresh cycles on the eisa/isa bus. the esc asserts the refresh y signal to indicate when a refresh cycle is in progress. refresh cycles are generated by two sources: the refresh unit inside the esc or an external isa bus masters. the eisa bus controller will enable the address lines la [ 15:2 ] and the be [ 3:0 ] y . the high and low page register contents will also be placed on the la [ 31:16 ] bus during refresh. memory slaves on the eisa/isa bus must not drive any data onto the data bus during the refresh cycle. slow memory slaves on the eisa/isa may extend the refresh cycle by negating the exrdy or chrdy signal respectively. the refresh cycles are also described in section 6.11. 5.9 eisa slot support the esc support up of 8 eisa slots. the esc provides support for the 8 slots as follows: # the esc address and data output buffers directly drive 240 pf capacitive load on the bus. # the esc generates slot specific aenx signals. # the esc supports eisa masters in all 8 slots. the esc generates encoded aens and encoded master acknowledge signals for 8 slots and 8 masters. these signals must to decoded on the system board to generate the slot specific aenx signals and mackx y signals. the esc can be programmed through mode select register bit [ 1:0 ] to directly generate these signals for 4 slots and 4 masters. 5.9.1 aen generation the esc directly generates the slot specific aen signals if the esc is configured to support 4 aenx (table 12). if the esc is programmed to support more than 4 eisa aenx, the esc will generate encoded aen signals. discrete logic like a f138 is required to generate the slot specific aens. 126
82374eb/82374SB table 12. aen generation cycle a [ 15:12 ] a [ 11:8 ] a [ 7:4 ] a [ 3:0 ] aen4 aen3 aen2 aen1 dma xxxx xxxx xxxx xxxx 1 1 1 1 io 0000 xx00 xxxx xxxx 1 1 1 1 io 0001 xx00 xxxx xxxx 1 1 1 0 io 0010 xx00 xxxx xxxx 1 1 0 1 io 0011 xx00 xxxx xxxx 1 0 1 1 io 0100 xx00 xxxx xxxx 0 1 1 1 io 0101-1111 xx00 xxxx xxxx 1 1 1 1 io xxxx xx01 xxxx xxxx 0 0 0 0 io xxxx xx10 xxxx xxxx 0 0 0 0 io xxxx xx11 xxxx xxxx 0 0 0 0 mem xxxx xxxx xxxx xxxx 0 0 0 0 table 13. encoded aen (aen) generation cycle a [ 15:12 ] a [ 11:8 ] a [ 7:4 ] a [ 3:0 ] eaen4 eaen3 eaen2 eaen1 dma xxxx xxxx xxxx xxxx 1 1 1 1 io 0000 xx00 xxxx xxxx 1 1 1 1 io 0001 xx00 xxxx xxxx 0 0 0 1 io 0010 xx00 xxxx xxxx 0 0 1 0 io 0011 xx00 xxxx xxxx 0 0 1 1 io 0100 xx00 xxxx xxxx 0 1 0 0 io 0101 xx00 xxxx xxxx 0 1 0 1 io 0110 xx00 xxxx xxxx 0 1 1 0 io 0111 xx00 xxxx xxxx 0 1 1 1 io 1000 xx00 xxxx xxxx 1 0 0 0 io 1001-1111 xx00 xxxx xxxx 1 1 1 1 io xxxx xx01 xxxx xxxx 0 0 0 0 io xxxx xx10 xxxx xxxx 0 0 0 0 io xxxx xx11 xxxx xxxx 0 0 0 0 mem xxxx xxxx xxxx xxxx 0 0 0 0 note: eaen [ 4:1 ] combinations not specified in the table are reserved. 127
82374eb/82374SB 5.9.2 mackx y generation the esc generates the eisa master acknowledge signals if the esc is configured for to directly support 4 masters through mode select register bit [ 1:0 ] . in this case the esc generates mackx y s for master 0-3. if the esc is programmed to support more than 4 eisa slots, the esc will generate encoded (e)mackx y s. discrete logic like a f138 is required to generate the mackx y s for the masters. table 14. encoded mack y (emackx y ) generation emack [ 4:1 ] mack7 y mack6 y mack5 y mack4 y mack3 y mack2 y mack1 y mack0 y 0000 1 1 1 1 1 1 1 0 0001 1 1 1 1 1 1 0 1 0010 1 1 1 1 1 0 1 1 0011 1 1 1 1 0 1 1 1 0100 1 1 1 0 1 1 1 1 0101 1 1 0 1 1 1 1 1 0110 1 0 1 1 1 1 1 1 0111 0 1 1 1 1 1 1 1 1111 1 1 1 1 1 1 1 1 note: emack [ 4:1 ] combinations 1000 1110 are reserved. 6.0 dma controller 6.1 dma controller overview the dma circuitry incorporates the functionality of two 82c37 dma controllers with seven independently programmable channels, (channels 0-3 and channels 5-7). dma channel 4 is used to cascade the two controllers together and will default to cascade mode in the mode register. in addition to accepting requests from dma slaves, the dma also responds to requests that are initiated by software. software may initiate a dma service request by setting any dma channel request register bit to a 1. the dma controller for channels 0-3 is referred to as ``dma-1'' and the controller for channels 4-7 is ``dma-2''. 128
82374eb/82374SB 290476 72 figure 9. internal dma controller each dma channel can be programmed for 8- or 16-bit dma device size. each channel can also be pro- grammed for compatibility, type ``a'', type ``b'', or type ``c''(burst transfer) timings. each dma channel defaults to the pc-at compatible settings for dma device size: channels [ 3:0 ] default to 8-bit, count-by-bytes transfers, while channels [ 7:5 ] default to 16-bit, count-by-words (address shifted) transfers. the esc provides the timing control and data size translation necessary for dma transfers between eisa/isa agents of mis- matched bus sizes. the dma controller supports full 32-bit addressing. each channel includes a 16-bit isa compatible current register which holds the 16 least-significant bits of the 32-bit address, and an isa compatible low page register which contains the eight second most significant bits. an additional high page register contains the eight most significant bits of the 32-bit address. the address counter can be programmed as either 16-bit compatible address counter or a full 32-bit address counter. the channels can also be programmed for any of four transfer modes. the transfer modes include single, block, demand, or cascade. each of the three active transfer modes (single, block, and demand), can perform three different types of transfers (read, write, or verify). the dma controller also features refresh address generation, and auto-initialization following a dma termina- tion. eisa compatible buffer chaining is included as well as stop registers to support ring buffer structures. scatter-gather reduces cpu overhead by eliminating reprogramming of the dma and i/o between buffers as well as reducing the number of interrupts. the dma controller includes the eisa bus arbiter which works with the pceb's pci bus arbiter. the arbiter determines which requester from among the requesting dma slaves, eisa bus masters, the pci bus, or refresh should have the bus. 129
82374eb/82374SB the dma controller is at any time either in master mode or slave mode. in master mode, the dma controller is either servicing a dma slave's request for dma cycles, allowing an isa master to use the bus via a cascaded dreq signal, or granting the bus to an eisa master via mreq y /mack y . in slave mode, the esc monitors both the eisa bus decoding and responding to i/o read and write commands that address its registers. when the dma is in master mode and servicing a dma slave, it works in conjunction with the esc eisa bus controller to create bus cycles on the eisa bus. the dma places addresses onto the internal address bus and the bus controller informs the dma when to place a new address on the internal bus. 6.2 dma transfer modes the channels can be programmed for any of four transfer modes. the transfer modes include single, block, demand, or cascade. each of the three active transfer modes (single, block, and demand), can perform three different types of transfers (read, write, or verify). the esc does not support memory to memory transfers. 6.2.1 single transfer mode in single transfer mode the dma is programmed to make one transfer only. the byte/word count will be decremented and the address decremented or incremented following each transfer. when the byte/word count ``rolls over'' from zero to ffffffh, or an external eop is encountered, a terminal count (tc) will load a new buffer via scatter-gather, buffer chaining or autoinitialize if it is programmed to do so. dreq must be held active until dack becomes active in order to be recognized. if dreq is held active throughout the single transfer, the bus will be released to the cpu after a single transfer. with the dreq asserted high, the dma i/o device will rearbitrate for the bus. upon winning the bus, another single transfer will be performed. this allows other bus masters a chance to arbitrate for, win, and execute cycles on the eisa bus. 6.2.2 block transfer mode in block transfer mode the dma is activated by dreq to continue making transfers during the service until a tc, caused by either a byte/word count going to ffffffh or an external eop, is encountered. dreq need only be held active until dack becomes active. if the channel has been programmed for it, a new buffer will be loaded by buffer chaining or auto-initialization at the end of the service. in this mode, it is possible to lock out other devices for a period of time (including refresh) if the transfer count is programmed to a large number and compatible timing is selected. block mode can effectively be used with type ``a'', type ``b'', or burst timing since the channel can be interrupted through the 4 m s timeout mechanism, and other devices (or refresh) can arbitrate for and win the bus. see section 7.0 on the eisa bus arbitration for a detailed description of the 4 m s timeout mechanism. note that scatter-gather block mode is not supported. 6.2.3 demand transfer mode in demand transfer mode the dma channel is programmed to continue making transfers until a tc (terminal count) is encountered or an external eop is encountered, or until the dma i/o device pulls dreq inactive. thus, transfers may continue until the i/o device has exhausted its data capacity. after the i/o device catches up, the dma service is re-established when the dma i/o device reasserts the channel's dreq. during the time between services when the system is allowed to operate, the intermediate values of address and byte/ word count are stored in the dma controller current address and current byte/word count registers. a tc can cause a new buffer to be loaded via scatter-gather, buffer chaining or autoinitialize at the end of the service if the channel has been programmed for it. 130
82374eb/82374SB 6.2.4 cascade mode this mode is used to cascade more than one dma controller together for simple system dma requests for the additional device propagate through the priority network circuitry of the preceding device. the priority chain is preserved and the new device must wait for its turn to acknowledge requests. within the esc architecture, channel 0 of dma controller two (dma-2, ch 4) is used to cascade dma controller one (dma-1) to provide a total of seven dma channels. channel 0 on dma-2 (labeled ch 4 overall) connects the second half of the dma system. this channel is not available for any other purpose. in cascade mode, the dma controller will respond to dreq with dack, but the esc will not drive the bus. cascade mode is also used to allow direct access of the system by 16-bit bus masters. these devices use the dreq and dack signals to arbitrate for the system bus and then they drive the address and command lines to control the bus. the isa master asserts its isa master request line (dreqx) to the dma internal arbiter. if the isa master wins the arbitration, the esc responds with an isa master acknowledge (dackx) signal active. upon sampling the dackx line active, the isa master asserts master16 y signal and takes control of the eisa bus. the isa master has control of the eisa bus, and the isa master may run cycles until it negates the master16 y signal. 6.3 dma transfer types each of the three active transfer modes (single, block, or demand) can perform three different types of transfers. these transfers are read, write and verify. write transfer write transfers move data from an eisa/isa i/o device to memory located on eisa/isa bus or pci bus. the dma indicates the transfer type to the eisa bus controller. the bus controller will activate iorc y and the appropriate eisa control signals (m/io y and w/r y ) to indicate a memory write. read transfer read transfers move data from eisa/isa or pci memory to an eisa/isa i/o device. the dma indicates the transfer type to the eisa bus controller. the bus controller will activate iowc y and the appropriate eisa control signals (m/io y and w/r y ) to indicate a memory read. verify transfer verify transfers are pseudo transfers. the dma controller operates as in read or write transfers, generating addresses and producing tc, etc. however, the esc does not assert the memory and i/o control signals. only the dack signals are asserted. internally the dma controller will count bclks so that the dack signals have a defined pulse width. this pulse width is nine bclks long. if verify transfers are repeated during block or demand dma requests, each additional pseudo transfer will add eight bclks. the dack signals will not be toggled for repeated transfers. 6.4 dma timing the esc dma provides four transfer timings. in addition to the compatible timings, the esc dma provides type ``a'', type ``b'', and type ``c'' (burst) timings for i/o slave devices capable of running at faster speeds. 131
82374eb/82374SB 6.4.1 compatible timings compatible timing is provided for dma slave devices. compatible timing runs at 9 bclks (1080 ns/single cycle) and 8 bclks (960 ns/cycle) during the repeated portion of a block or demand mode transfers. 290476 73 figure 10. compatible dma read transfer (8 bclks) 290476 74 figure 11. compatible dma write transfer (8 bclks) 132
82374eb/82374SB 6.4.2 type ``a'' timing type ``a'' timing is provided to allow shorter cycles to eisa memory. (note: main memory behaves like eisa memory because the pceb has an eisa slave interface.) type ``a'' timing runs at 7 bclks (840 ns/single cycle) and 6 bclks (720 ns/cycle) during the repeated portion of a block or demand mode transfer. type ``a'' timing varies from compatible timing primarily in shortening the memory operation to the minimum allowed by system memory. the i/o portion of the cycle (data setup on write, i/o read access time) is the same as with compatible cycles. the actual active command time is shorter, but it is expected that the dma devices which provide the data access time or write data setup time should not require excess iorc y or iowc y command active time. because of this, most dma devices should be able to use type ``a'' timing. 290476 75 figure 12. type ``a'' dma read transfers (6 bclks) 133
82374eb/82374SB 6.4.3 type ``b'' timing type ``b'' timing is provided for 8-/16-bit dma devices which can accept faster i/o timing. type ``b'' only works with fast system memory. type ``b'' timing runs at 6 bclks (720 ns/single cycle) and 4 bclks (480 ns/ cycle) during the repeated portion of a block or demand mode transfer. type ``b'' timing requires faster dma slave devices than compatible timing in that the cycles are shortened so that the data setup time on i/o write cycles is shortened and the i/o read access time is required to be faster. some of the current isa devices should be able to support type ``b'' timing, but these will probably be more recent designs using relatively fast technology. 290476 76 figure 13. type ``b'' dma read transfer (4 bclks) 134
82374eb/82374SB 6.4.4 type ``c'' (burst) timing type ``c'' (burst) timing is provided for eisa dma devices. the dma slave device needs to monitor exrdy and iorc y or iowc y signals to determine when to change the data (on writes) or sample the data (on reads). this timing will allow up to 33 mbytes per second transfer rate with a 32-bit dma device and 32-bit memory. note that 8- or 16-bit dma devices are supported (through the programmable dma address incre- ment) and that they use the ``byte lanes'' natural to their size for the data transfer. as with all bursts, the system will revert to two bclk cycles if the memory does not support burst. when a dma burst cycle accesses non-burst memory and the dma cycle crosses a page boundary into burstable memory, the esc will continue performing standard (non-burst) cycles. this will not cause a problem since the data is transferred correctly. 290476 77 figure 14. type ``c'' (burst) dma read transfers (1 bclk) 6.5 channel priority for priority resolution the dma consists of two logical channel groups-channels 0-3 and channels 4-6. each group may be in either fixed or rotate mode, as determined by the command register. for arbitration purposes, the source of the dma request is transparent. dma i/o slaves normally assert their dreq line to arbitrate for dma service. however, a software request for dma service can be presented through each channel's dma request register. a software request is subject to the same prioritization as any hardware request. please see the detailed register description in section 3.0 for request register program- ming information. 135
82374eb/82374SB fixed priority the initial fixed priority structure is as follows: high priority low priority (0, 1, 2, 3) 5, 6, 7 the fixed priority ordering is 0, 1, 2, 3, 5, 6, and 7. in this scheme, channel 0 has the highest priority, and channel 7 has the lowest priority. channels [ 3:0 ] of dma-1 assume the priority position of channel 4 in dma- 2, thus taking priority over channels 5, 6, and 7. rotating priority rotation allows for ``fairness'' in priority resolution. the priority chain rotates so that the last channel serviced is assigned the lowest priority in the channel group (0-3, 5-7). channels 0-3 rotate as a group of 4. they are always placed between channel 5 and channel 7 in the priority list. channel 5-7 rotate as part of a group of 4. that is, channels (5-7) form the first three partners in the rotation, while channel group (0-3) comprises the fourth position in the arbitration. table 15 demonstrates rotation priority: table 15. rotating priority example programmed mode action priority high low group (0-3) is in rotation mode 1) initial setting (0, 1, 2, 3), 5, 6, 7 group (4-7) is in fixed mode. 2) after servicing channel 2 (3, 0, 1, 2), 5, 6, 7 3) after servicing channel 3 (0, 1, 2, 3), 5, 6, 7 group (0-3) in rotation mode 1) initial setting (0, 1, 2 3), 5, 6, 7 group (4-7) is in rotation mode 2) after servicing channel 0 5, 6, 7, (1, 2, 3, 0) 3) after servicing channel 5 6, 7, (1, 2, 3, 0), 5 (note that the first servicing of 4) after servicing channel 6 7, (1, 2, 3, 0), 5, 6 channel 0 caused double rotation). 5) after servicing channel 7 (1, 2, 3, 0), 5, 6, 7 6.6 scatter-gather functional description scatter-gather provides the capability of transferring multiple buffers between memory and i/o without cpu intervention. in scatter-gather, the dma can read the memory address and word count from an array of buffer descriptors called the scatter-gather descriptor (sgd) table. this allows the dma to sustain dma transfers until all buffers in the scatter-gather descriptor table are transferred. the scatter-gather command register and scatter-gather status register are used to control the operational aspect of scatter-gather transfers (see section 3.2 for details of these registers). the scatter-gather descrip- tor next link register holds the address of the next buffer descriptor in the scatter-gather descriptor table. the next buffer descriptor is fetched from the scatter-gather descriptor table by a dma read transfer. dack y will not be asserted for this transfer because the i/o device is the dma itself and the dack is internal to the esc. the esc will assert iowc y for these bus cycles like any other dma transfer. the esc will behave as an 8-bit i/o slave and will run type ``b'' timings for a scatter-gather buffer descriptor transfer. eop will be asserted at the end of the transfer. 136
82374eb/82374SB to initiate a typical scatter-gather transfer between memory and an i/o device the following steps are involved: 1. software prepares a scatter-gather descriptor (sgd) table in system memory. each scatter-gather de- scriptor is 8 bytes long and consists of an address pointer to the starting address and the transfer count of the memory buffer to be transferred. in any given sgd table, two consecutive sgds are offset by 8 bytes and are aligned on a 4-byte boundary. 2. each scatter-gather descriptor for the linked list must contain the following information: a. memory address (buffer start) 4 bytes b. byte count (buffer size) 3 bytes c. end of link list 1 bit (msb) 290476 78 figure 15. scatter-gather descriptor format 3. initialize dma mode and extended mode registers with transfer specific information like 8-/16-bit i/o device, transfer mode, transfer type, etc. 4. software provides the starting address of the scatter-gather descriptor table by loading the scatter-gather descriptor table pointer register. 5. engage the scatter-gather machine by writing a start command to the scatter-gather command register. 6. the mask register should be cleared as last the last step of programming the dma register set. this is to prevent dma from starting a transfer with a partially loaded command description. 7. once the register set is loaded and the channel is unmasked, the dma will generate an internal request to fetch the first buffer from the scatter gather descriptor table. 8. the dma will then respond to dreq or software requests. the first transfer from the first buffer will move the memory address and word count from the base register set to the current register set. as long as scatter-gather is active and the base register set is not loaded and the last buffer has not been fetched, the channel will generate a request to fetch a reserve buffer into the base register set. the reserve buffer is loaded to minimize latency problems going from one buffer to another. fetching a reserve buffer has a lower priority than completing dma for the channel. 9. the dma controller will terminate a scatter-gather cycle by detecting an end of list (eol) bit in the sgd. after the eol bit is detected, the channel will transfer the buffers in the base and current register sets if they are loaded. at terminal count the channel will assert eop or irq13 depending on its programming and set the terminate bit in the scatter-gather status register. the active bit in the scatter-gather status register will be reset and the channel's mask bit will be set. 137
82374eb/82374SB 290476 79 figure 16. link list example 6.7 register functionality see section 3.2 for detailed information on register programming, bit definitions, and default values/functions after a reset. dma channel 4 is used to cascade the two dma controllers together and should not be programmed for any mode other than cascade. the mode register for channel 4 will default to cascade mode. special attention should also be take when programming the command and mask registers as related to channel 4 (refer to the command and mask register descriptions, section 3.2). 6.7.1 address compatibility mode whenever the dma is operating in address compatibility mode, the addresses do not increment or decrement through the high and low page registers, and the high page register is set to 00h. this is compatible with the 82c37 and low page register implementation used in the pc at. this mode is set when any of the lower three address bytes of a channel are programmed. if the upper byte of a channel's address is programmed last, the channel will go into extended address mode. in this mode, the high byte may be any value and the address will increment or decrement through the entire 32-bit address. 138
82374eb/82374SB after reset is negated all channels will be set to address compatibility mode. the dma master clear com- mand will also reset the proper channels to address compatibility mode. the address compatibility mode bits are stored on a per channel basis. 6.7.2 summary of the dma transfer sizes table 16 lists each of the dma device transfer sizes. the column labeled ``word count register'' indicates that the register contents represent either the number of bytes to transfer or the number of 16-bit words to transfer. the column labeled ``current address register increment/decrement'' indicates the number added to or taken from the current address register after each dma transfer cycle. the mode register determines if the current address register will be incremented or decremented. table 16. dma transfer size dma device date size and word count word count current address register increment/decrement 8-bit i/o, count by bytes bytes 1 16-bit i/o, count by words (address shifted) words 1 16-bit i/o, count by bytes bytes 2 32-bit i/o, count by bytes bytes 4 6.7.3 address shifting when programmed for 16-bit i/o count by words to maintain compatibility with the implementation of the dma in the pc/at which used the 82c37, the dma will shift the addresses when the extended mode register is programmed for, or defaulted to, transfers to/from a 16-bit device count6.7.3-by-words. note that the least significant bit of the low page register is dropped in 16-bit shifted mode. when programming the current address register while the dma channel is in this mode, the current address must be programmed to an even address with the address value shifted right by one bit. the address shifting is as shown in table 17. table 17. address shifting in 16-bit i/o dma transfers output 8-bit i/o 16-bit i/o 16-bit i/o 32-bit i/o address programmed programmed programmed programmed address address (shifted) address (no shift) address (no shift) a0 a0 ``0'' a0 a0 [ 16:1 ] a [ 16:1 ] a [ 15:0 ] a [ 16:01 ] a [ 16:01 ] a [ 31:17 ] a [ 31:17 ] a [ 31:17 ] a [ 31:17 ] a [ 31:17 ] note: the least significant bit of the low register is dropped in 16-bit shifted mode. 6.7.4 stop registers (ring buffer data structure) to support a common data communication data structure, (the ring buffer), a set of dma registers have been provided. these registers are called stop registers. each channel has 22-bits of register location associated with it. the 22-bits are distributed between three different registers (one 8-bit and two 8-bit). the stop registers can be enabled or disabled by writing to the channel's corresponding extended mode register. the ring buffer data structure reserves a fixed portion of memory, on dword boundaries, to be used for a dma channel. consecutively received frames or other data structures are stored sequentially within the boundaries of the ring buffer memory. 139
82374eb/82374SB the beginning and end of the ring buffer area is defined in the base address register and the base address register a the base byte/transfer count. the incoming frames (data) are deposited in sequential locations of the ring buffer. when the dma reaches the end of the ring buffer, indicating the byte count has expired, the dma controller (if so programmed) will autoinitialize. upon autoinitialization, the current address register will be restored from the base address register, taking the process back to the start of the ring buffer. the dma will then be available to begin depositing the incoming bytes in the ring buffers sequential locations, providing that the cpu has read the data that was previously placed in those locations. the dma determines that the cpu has read certain data by the value that the cpu writes into the stop register. once the data of a frame is read by the cpu, the memory location it occupies becomes available for other incoming frames. the stop register prevents the dma from over writing data that has not yet been read by the cpu. after the cpu has read a frame from memory it will update the stop register to point to the location that was last read. the dma will not deposit data into any location beyond that pointed to by the stop register. the last address transferred before the channel is masked is the first address that matches the stop register. for example, if the stop register e 00001ch, the last three transfers are shown in table 18. table 18. stop register functionality example by bytes by words by words increment xx00001ah xx000018h xx000018h xx00001bh xx00001ah xx00001ah xx00001ch xx00001ch xx00001ch decrement xx000021h xx000023h xx000023h xx000020h xx000021h xx000021h xx00001fh xx00001fh xx00001fh note: the stop registers store values to compare against la [ 23:2 ] only, so the size of the ring buffer is limited to 16 mbytes. 6.7.5 buffer chaining mode and status registers the chaining mode registers are used to implement the buffer chaining mode of a channel. the buffer chaining mode is useful when transferring data from a peripheral to several different areas of memory with one continuous transfer operation. four registers are used to implement this function: the chaining mode register, the chaining mode status register, the channel interrupt status register, and the chain buffer expiration control register. the chaining mode register controls the buffer chaining initialization. buffer chaining mode can be enabled or disabled. a chaining mode bit is used to indicate if base register programming is complete and chaining can begin, or to hold off chaining because the base registers still need programming. another bit dictates the buffer expiration response by indicating whether an irq13 or eop should be issued when the buffer needs reprogramming. the chaining mode status register indicates whether each channel's chaining mode is en- abled or disabled. the channel interrupt status register indicates the channel source of a dma chaining interrupt on irq13. the cpu can read this register to determine which channel asserted irq13 following a buffer expiration. the chain buffer expiration control register is a read only register that reflects the outcome after the expiration of a chain buffer. if a channel bit is set to 0, irq13 will be activated following the buffer expiration. if a channel bit is set to 1, eop will be asserted following the buffer expiration. 140
82374eb/82374SB 6.7.6 autoinitialize by programming a bit in the mode register, a channel may be set up as an autoinitialize channel. during autoinitialization, the original values of the current page, current address and current byte/word count registers are automatically restored from the base address, and word count registers of that channel following tc. the base registers are loaded simultaneously with the current registers by the microprocessor and remain unchanged throughout the dma service. the mask bit is not set when the channel is in autoinitialize. following autoinitialize the channel is ready to perform another dma service, without cpu intervention, as soon as a valid dreq is detected. (note: autoinitialize will not function if the channel is also programmed for scatter- gather or buffer chaining. only one of these features should be enabled at a time.) 6.8 software commands these are additional special software commands which can be executed in the program condition. they do not depend on any specific bit pattern on the data bus. the three software commands are: 1. clear byte pointer flip-flop. 2. master clear. 3. clear mask register. 6.8.1 clear byte pointer flip-flop this command is executed prior to writing or reading new address or word count information to the dma. this initializes the flip-flop to a known state so that subsequent accesses to register contents by the microproces- sor will address upper and lower bytes in the correct sequence. when the cpu is reading or writing dma registers, two byte pointer flip-flops are used; one for channels 0-3 and one for channels 4-6. both of these act independently. there are separate software commands for clearing each of them (0ch for channels 0-3, 0d8h for channels 4-7). an additional byte pointer flip-flop has been added for use when eisa masters are reading and writing dma registers. (the arbiter state will be used to determine the current master of the bus.) this flip-flop is cleared when an eisa master performs a write to either 00ch or 0d8h. there is one byte pointer flip flop per eight dma channels. this byte pointer was added to eliminate the problem of the cpu's byte pointer getting out of synchronization if an eisa master takes the bus during the cpu's dma programming. 6.8.2 dma master clear this software instruction has the same effect as the hardware reset. the command, status, request, and internal first/last flip-flop registers are cleared and the mask register is set. the dma controller will enter the idle cycle. there are two independent master clear commands, 0dh which acts on channels 0-3, and 0dah which acts on channels 4-6. 6.8.3 clear mask register this command clears the mask bits of all four channels, enabling them to accept dma requests. i/o port 00eh is used for channels 0-3 and i/o port 0dch is used for channels 4-6. 141
82374eb/82374SB 6.9 terminal count/eop summary table 19 is a summary of the events that happen as a result of a terminal count or external eop when running dma in various modes. table 19. terminal count/eop summary table conditions autoinit no yes event word counter expired yes x yes x eop input x asserted x asserted result status tc set set set set mask set set e e sw request clr clr clr clr current register e e load load notes: 1. load e load current from base 2. ``-'' e no change 3. x e don't care 4. clr e clear 6.10 buffer chaining the buffer chaining mode of a channel is useful for transferring data from a peripheral to several different areas of memory within one transfer operation (from the dma device's viewpoint). this is accomplished by causing the dma to interrupt the cpu for more programming information while the previously programmed transfer is still in progress. upon completion of the previous transfer, the dma controller will then load the new transfer information automatically. in this way, the entire transfer can be completed without interrupting the operation of the dma device. this mode is most useful for dma single-cycle or demand modes where the transfer process allows time for the cpu to execute the interrupt routine. the buffer chaining mode of a channel may be entered by programming the address and count of a transfer as usual. after the initial address and count is programmed, the base registers are selected via the chaining mode register chaining mode enabled bit. the address and count for the second transfer and both the chaining mode enabled and the program complete bit of the chaining mode register should be programmed at this point, before starting the dma process. when, during the dma process, the current buffer is expired, the base address, page, and count registers will be transferred to the current registers and a signal that the buffer has been expired is sent to the programming master. this signal will be an irq13 if the master is the cpu, or a tc if the programming master is an eisa master device. the type of programming master is indicated in the dma's chaining mode register, bit 4. if the cpu is the programming master for the channel, tc will be generated only if the current buffer expires and there is no next buffer stored in the base registers. 142
82374eb/82374SB upon the expiration of a current buffer, the new base register contents should be programmed and both the chaining mode enabled and program complete bits of the chaining mode register should be set. this resets the interrupt, if the cpu was the programming master, and allows for the next base register to current register transfer. if the program complete bit is not set before the current transfer reaches tc, then the dma controller will set the mask bit and the tc bit in the status register and stop transferring data. in this case, an over-run is likely to occur. to determine if this has, a read of either status register or the mask register can be done (the mask register has been made readable). if the channel is masked or has registered a tc, the dma channel has been stopped and the full address, count, and chaining mode must be programmed to return to normal operation. note that if the cpu is the programming master, an interrupt will only be generated if a current buffer expires and chaining mode is enabled. it will not occur during initial programming. the channel interrupt status register will indicate pending interrupts only. that is, it will indicate an empty base register with chaining mode enabled. when chaining mode is enabled, only the base registers are written by the processor, and only the current registers can be read. the current registers are only updated on a tc. 6.11 refresh unit the esc provides an eisa bus compatible refresh unit that provides 14 bits of refresh address for eisa/isa bus drams that do not have their own local refresh units. the refresh system uses the combined functions of the interval timers, the dma arbiter, dma address counter, and eisa bus controller. functionally, the re- fresh unit is a sub-section of the esc dma unit. the dma address counter is used to increment the refresh address register following each refresh cycle. interval counter 1, timer 1 generates an internal refresh re- quest. the dma arbiter detects a refresh signal from either the counter/timer or the refresh y input and determines when the refresh will be done. the dma drives the refresh address out onto the la address bus. the cycle is decoded and driven onto the eisa address bus by the eisa bus controller. the esc eisa bus controller is responsible for generating the eisa cycle control signals. timer 1 counter 1 should be pro- grammed to provide a refresh request about every 15 m s. requests for refresh cycles are generated by two sources: the esc (timer 1 counter 1), and 16-bit masters that activate refresh y when they own the eisa bus. if a 16-bit isa bus master holds the bus longer than 15 m s, it must initiate memory refresh cycles. if the isa master initiates a refresh cycle while it owns the bus, it floats the address lines and cycle control signals and asserts refresh y to the esc. the esc eisa bus controller generates the cycle control signals and the esc dma refresh unit supplies the refresh address. the isa master must then wait one bclk after mrdc y is negated before floating refresh y and driving the address lines and control signals. typically, the refresh cycle length is five bclk's. the i/o slave can insert one wait state to extend the cycle to six bclk's by asserting chrdy. the esc eisa bus controller, upon seeing refresh y , knows to run refresh cycles instead of dma cycles. 7.0 eisa bus arbitration the esc receives requests for eisa bus ownership from several different sources; from dma devices, from the refresh counter, from eisa masters and from pci agents. pci agents requesting the eisa bus request the eisa bus through the pceb. additionally, 16-bit isa masters may request the bus through a cascaded dma channel (see the cascade mode description in section 6.2.4). 143
82374eb/82374SB 7.1 arbitration priority at the top level of the arbiter, the esc uses a three way rotating priority arbitration method. on a fully loaded bus, the order in which the devices are granted bus access is independent of the order in which they assert a bus request, since devices are serviced based on their position in the rotation. the arbitration scheme assures that dma channels and eisa masters are able to access the bus with minimal latency. the pceb and eisa masters share one of the slots in the three way rotating priority scheme. this sharing is a two way rotation between the cpu and eisa masters as a group. in this arbitration scheme, the pceb acts on behalf of the cpu and all other pci masters. eisa masters have a rotating priority structure which can handle up to eight master requests. the next position in the top level arbiter is occupied by the dma. the dma's dreq lines can be placed in either fixed or rotating priority. the default mode is fixed and by programming the dma command registers, the priority can be modified to rotating priority mode. 7.2 preemption an eisa compatible arbiter ensures that minimum latencies are observed for both eisa dma devices, and eisa masters. 7.2.1 pceb eisa bus acquisition and pceb preemption eisa bus arbitration is intended to be optimized for cpu access the eisa bus. since the cpu accesses to the eisa bus through the pceb, the pceb is assumed to be the default owner of the eisa bus. the arbitration interface between the pceb and the esc is implemented as a hold/hlda (eisahold/ eisahlda) pair. if a pci cycle requires access to the eisa bus while eisahlda signal is asserted (eisa bus busy) the pci cycle is retried, and the pceb requests the eisa bus by asserting pereq y . the esc, after sampling per- eq y asserted, preempts the current owner of the eisa bus. the esc grants the eisa bus by negating eisahold signal. the esc asserts eisahold to the pceb when the esc needs to acquire the ownership of the eisa bus. while eisahold is asserted, the arbitration process is dynamic and may change (i.e. the esc is still accept- ing eisa bus requests). when the pceb returns eisahlda, the arbiter freezes the arbitration process and determine the winner. if the new winner is an eisa master or dma channel, the esc will assert nmflush y . the esc tri-states the nmflush y output driver on the following clock. the pceb holds nmflush y assert- ed until all buffers are flushed. after all buffers are flushed, the pceb negates nmflush y and then tri-state the output buffer. after sampling nmflush y negated, the esc resumes driving nmflush y on the next pci clock. this way the esc does not assert mack y or dack y until the pceb acknowledges that all line buffers have been flushed. 144
82374eb/82374SB 290476 80 figure 17. eisa arbitration 290476 81 figure 18. pceb preemption 145
82374eb/82374SB 7.2.2 eisa master preemption eisa specification requires that eisa masters must release the bus within 64 bclks (8 m s) after the esc negates mackx y . if the bus master attempts to start a new bus cycle after this timeout period, a bus timeout (nmi) is generated and the rstdrv is asserted to reset the offending bus master. 7.2.3 dma preemption a dma slave device that is not programmed for compatible timing is preempted from the eisa bus by another device that requests use of the bus. this will occur regardless of the priority of the pending request. for dma devices not using compatible timing mode, the dma controller stops the dma transfer and releases the bus within 32 bclk (4 m s) of a preemption request. upon the expiration of the 4 m s timer, the dack is negated after the current dma cycle has completed. the eisa bus then arbitrated for and granted to the highest priority requester. this feature allows flexibility in programming the dma for long transfer sequences in a performance timing mode while guaranteeing that vital system services such as refresh are allowed access to the expansion bus. the 4 m s timer is not used in compatible timing mode. it is only used for dma channels programmed for type ``a'', type ``b'', or type ``c'' (burst) timing. the 4 m s timer is also not used for 16-bit isa masters cascaded through the dma dreq lines. if the dma channel that was preempted by the 4 m s timer is operating in block mode, an internal bit will be set so that the channel will be arbitrated for again, independent of the state of dreq. 7.3 slave timeouts a slave which does not release exrdy or chrdy can cause the cmd y active time to exceed 256 bclks (32 m s). the esc does not monitor exrdy or chrdy for this timeout. typically this function is provided in a system through a third party add-in card. the add-in cards which monitor exrdy or chrdy assert iochk signal when the 256 bclk count expires. the esc in response asserts nmi. the only way that a 16-bit isa master can be preempted from the eisa bus is if it exceeds the 256 bclk (32 m s) limit on cmd y active. 7.4 arbitration during non-maskable interrupts if a non-maskable interrupt (nmi) is pending at the pceb, and the pceb is requesting the bus, the dma and eisa masters will be bypassed each time they come up for rotation. this gives the pceb the eisa bus bandwidth on behalf of the cpu to process the interrupt as fast as possible. 8.0 interval timers the esc contains five counter/timers that are equivalent to those found in the 82c54 programmable interval timer. the five counters are contained in two separate esc timer units, referred to as timer-1 and timer-2. the esc uses the timers to implement key eisa system functions. timer-1 contains three counters, and timer-2 contains two counters. eisa systems do not use the middle counter on timer-2. interval timer 1, counter 0 is connected to the interrupt controller irq0 and provides a system timer interrupt for a time-of-day, diskette time-out, or other system timing functions. counter 1 generates a refresh-request signal and counter 2 generates the tone for the speaker. 146
82374eb/82374SB interval timer 2, counter 0 implements a fail safe timer. counter 0 generates nmi at regular intervals, thus preventing the system from locking up. counter 1 is not used. counter 2 is used to slow down the cpu by means of pulse-width modulation. the output of timer 2 counter 2 is tied to the slowh y signal. table 20. interval timer functions function counter 0 system timer counter 0 fail-safe timer gate always on always on clock in 1.193 mhz(osc/12) 0.298 mhz(osc/48) out int-1 irq0 nmi interrupt counter 1 refresh request gate always on clock in 1.193 mhz(0sc/12) out refresh request counter 2 counter 2 gate programmable refresh request clock in port 61h out 1.193 mhz(osc/12) 8 mhz (bclk) speaker cpu speed control (slowh y ) 8.1 interval timer address map table 21 shows the i/o address map of the interval timer counters: table 21. interval timer i/o address map i/o port address register description 040h timer 1, system timer (counter 0) 041h timer 1, refresh request (counter 1) 042h timer 1, speaker tone (counter 2) 043h timer 1, control word register 048h timer 2, fail-safe timer (counter 0) 049h timer 2, reserved 04ah timer 2, cpu speed control (counter 2) 04bh timer 2, control word register timer 1ecounter 0, system timer this counter functions as the system timer by controlling the state of irq [ 0 ] and is typically programmed for mode 3 operation. the counter produces a square wave with a period equal to the product of the counter period (838 ns) and the initial count value. the counter loads the initial count value one counter period after software writes the count value to the counter i/o address. the counter initially asserts irq [ 0 ] and decre- ments the count value by two each counter period. the counter negates irq [ 0 ] when the count value reaches 0. it then reloads the initial count value and again decrements the initial count value by two each counter period. the counter then asserts irq [ 0 ] when the count value reaches ``0'', reloads the initial count value, and repeats the cycle, alternately asserting and negating irq [ 0 ] . 147
82374eb/82374SB timer 1ecounter 1, refresh request signal this counter provides the refresh request signal and is typically programmed for mode 2 operation. the counter negates refresh request for one counter period (833 ns) during each count cycle. the initial count value is loaded one counter period after being written to the counter i/o address. the counter initially asserts refresh request, and negates it for 1 counter period when the count value reaches 1. the counter then asserts refresh request and continues counting from the initial count value. timer 1ecounter 2, speaker tone this counter provides the speaker tone and is typically programmed for mode 3 operation. the counter provides a speaker frequency equal to the counter clock frequency (1.193 mhz) divided by the initial count value. the speaker must be enabled by a write to port 061h (see section 3.7 on the nmi status and control ports). timer 2ecounter 0, fail-safe timer this counter functions as a fail-save timer by preventing the system from locking up. this counter generates an interrupt on the nmi line as the count expires by setting bit 7 on port 0461h. software routines can avoid the fail-safe nmi by resetting the counter before the timer count expires. timer 2ecounter 2, cpu speed control this counter generates the slowh y to the cpu and is typically programmed for mode 1 operation. the counter is triggered by the refresh request signal generated by timer 1-counter 1 only. if the counter is programmed, the counters slowh y output will stop the cpu for the programmed period of the one-shot every time a refresh request occurs. this counter is not configured or programmed until a speed reduction in the system is required. 8.2 programming the interval timer the counter/timers are programmed by i/o accesses and are addressed as though they are contained in two separate 82c54 interval timers. timer 1 contains three counters and timer 2 contains two counters. each timer is controlled by a separate control word register. table 22 lists the six operating modes for the interval counters. note that for the fail safe timer (timer 2, counter 0), only mode 0 is supported. the interval timer is an i/o-mapped device. several commands are available: 1. the control word command specifies: e which counter to read or write e the operating mode e the count format (binary or bcd) 2. the counter latch command latches the current count so that it can be read by the system. the count- down process continues. 3. the read back command reads the count value, programmed mode, the current state of the out pins, and the state of the null count flag of the selected counter. 148
82374eb/82374SB the read/write logic selects the control word register during an i/o write when address lines a1, a0 e 11. this condition occurs during an i/o write to port addresses 043h and 04bh, the addresses for the control word register on timer 1 and control word register on timer 2 respectively. if the cpu writes to port 043h or port 04bh, the data is stored in the respective control word register and is interpreted as a control word used to define the operation of the counters. the control word register is write-only. counter status information is available with the read-back com- mand. table 22. counter operating modes mode function 0 out signal on end of count ( e 0) 1 hardware retriggerable one-shot 2 rate generator (divide by n counter) 3 square wave output 4 software triggered strobe 5 hardware triggered strobe because the timer counters come up in an unknown state after power up, multiple refresh requests may be queued up. to avoid possible multiple refresh cycles after power up, program the timer counter immediately after power up. write operations programming the interval timer is a simple process: 1. write a control word. 2. write an initial count for each counter. 3. load the least and/or most significant bytes (as required by control word bits 5, 4) of the 16-bit counter. the programming procedure for the esc timer units is very flexible. only two conventions need to be ob- served. first, for each counter, the control word must be written before the initial count is written. second, the initial count must follow the count format specified in the control word (least significant byte only, most significant byte only, or least significant byte and then most significant byte). since the control word register and the three counters have separate addresses (selected by the a1, a0 inputs), and each control word specifies the counter it applies to (sc0, sc1 bits), no special instruction sequence is required. any programming sequence that follows the conventions above is acceptable. a new initial count may be written to a counter at any time without affecting the counter's programmed mode in any way. counting will be effected as described in the mode definitions. the new count must follow the programmed count format. if a counter is programmed to read/write two-byte counts, the following precaution applies: a program must not transfer control between writing the first and second byte to another routine which also writes into that same counter. otherwise, the counter will be loaded with an incorrect count. interval timer control word format the control word specifies the counter, the operating mode, the order and size of the count value, and whether it counts down in a 16-bit or binary-coded decimal (bcd) format. after writing the control word, a new count may be written at any time. the new value will take effect according to the programmed mode. 149
82374eb/82374SB if a counter is programmed to read/write two-byte counts, the following precaution applies: a program must not transfer control between writing the first and second byte to another routine which also writes into that same counter. otherwise, the counter will be loaded with an incorrect count. the count must always be completely loaded with both bytes. read operations it is often desirable to read the value of a counter without disturbing the count in progress. this is easily done in the esc timer units. there are three possible methods for reading the counters: a simple read operation, the counter latch command, and the read-back command. counter i/o port read the first method is to perform a simple read operation. to read the counter the clk input of the selected counter must be inhibited by using either the gate input or external logic. otherwise, the count may be in the process of changing when it is read, giving an undefined result. when reading the count value directly, follow the format programmed in the control register: read lsb, read msb, or read lsb then msb. within the esc timer unit, the gate input on timer 1 counter 0, counter 1 and timer 2 counter 0 are tied high. therefore, the direct register read should not be used on these two counters. the gate input of timer 1 counter 2 is controlled through i/o port 061h. if the gate is disabled through this register, direct i/o reads of port 042h will return the current count value. counter latch command the counter latch command latches the count at the time the command is received. this command is used to insure that the count read from the counter is accurate (particularly when reading a two-byte count). the count value is then read from each counter's count register as was programmed by the control register. the selected counter's output latch (ol) latches the count at the time the counter latch command is received. this count is held in the latch until it is read by the cpu (or until the counter is reprogrammed). the count is then unlatched automatically and the ol returns to ``following'' the counting element (ce). this allows reading the contents of the counters ``on the fly'' without effecting counting in progress. multiple counter latch commands may be used to latch more than one counter. each latched counter's ol holds its count until it is read. counter latch commands do not effect the programmed mode of the counter in any way. the counter latch command can be used for each counter in the esc timer unit. if a counter is latched and then, some time later, latched again before the count is read, the second counter latch command is ignored. the count read will be the count at the time the first counter latch command was issued. with either method, the count must be read according to the programmed format; specifically, if the counter is programmed for two byte counts, two bytes must be read. the two bytes do not have to be read one right after the other; read, write, or programming operations for other counters may be inserted between them. another feature of the esc timer unit is that reads and writes of the same counter may be interleaved. for example, if the counter is programmed for two byte counts, the following sequence is valid: 1. read least significant byte. 2. write new least significant byte. 3. read most significant byte. 4. write new most significant byte. 150
82374eb/82374SB one precaution is worth noting. if a counter is programmed to read/write two-byte counts, a program must not transfer control between reading the first and second byte to another routine which also reads from that same counter. otherwise, an incorrect count will be read. read back command the third method uses the read-back command. the read-back command is used to determine the count value, programmed mode, and current states of the out pin and null count flag of the selected counter or counters. the read-back command is written to the control word register, which causes the current states of the above mentioned variables to be latched. the value of the counter and its status may then be read by i/o access to the counter address. the read-back command may be used to latch multiple counter output latches (ol) by setting the count y bit d5 e 0 and selecting the desired counter(s). this single command is functionally equivalent to several counter latch commands, one for each counter latched. each counter's latched count is held until it is read (or the counter is reprogrammed). once read, a counter is automatically unlatched. the other counters remain latched until they are read. if multiple count read-back commands are issued to the same counter without reading the count, all but the first are ignored; i.e. the count which will be read is the count at the time the first read-back command was issued. the read-back command may also be used to latch status information of selected counter(s) by setting status y bit d4 e 0. status must be latched to be read. the status of a counter is accessed by a read from that counter's i/o port address. if multiple counter status latch operations are performed without reading the status, all but the first are ignored. the status returned from the read is the counter status at the time the first status read-back command was issued. both count and status of the selected counter(s) may be latched simultaneously by setting both the count y and status y bits [ 5:4 ] e 00b. this is functionally the same as issuing two consecutive, separate read-back commands. the above discussions apply here also. specifically, if multiple count and/or status read-back commands are issued to the same counter(s) without any intervening reads, all but the first are ignored. if both count and status of a counter are latched, the first read operation from that counter will return the latched status, regardless of which was latched first. the next one or two reads (depending on whether the counter is programmed for one or two type counts) return the latched count. subsequent reads return un- latched count. 9.0 interrupt controller the esc provides an eisa compatible interrupt controller which incorporates the functionality of two 82c59 interrupt controllers. the two controllers are cascaded so that 14 external and two internal interrupts are possible. the master interrupt controller provides irq [ 7:0 ] and the slave interrupt controller provides irq [ 15:8 ] (figure 19). the two internal interrupts are used for internal functions only and are not available at the chip periphery. irq2 is used to cascade the two controllers together and irq0 is used as a system timer interrupt and is tied to interval timer 1, counter 0. the remaining 14 interrupt lines (irq1, irq3-irq15) are available for external system interrupts. edge or level sense selection is programmable on a by-controller basis. the interrupt controller consists of two separate 82c59 cores. interrupt controller 1 (cntrl-1) and interrupt controller 2 (cntrl-2) are initialized separately, and can be programmed to operate in different modes. the default settings are: 80x86 mode, edge sensitive (irq0-15) detection, normal eoi, non-buffered mode, special fully nested mode disabled, and cascade mode. cntrl-1 is connected as the master interrupt controller and cntrl-2 is connected as the slave interrupt controller. 151
82374eb/82374SB 290476 82 figure 19. block diagram of the interrupt controller table 23 lists the i/o port address map for the interrupt registers. table 23. i/o address map interrupts i/o address y of bits register irq [ 7:0 ] 0020h 8 cntrl-1 control register irq [ 7:0 ] 0021h 8 cntrl-1 mask register irq [ 7:0 ] 04d0h 8 cntrl-1 edge/level control register irq [ 15:8 ] 00a0h 8 cntrl-2 control register irq [ 15:8 ] 00a1h 8 cntrl-2 mask register irq [ 15:8 ] 04d1h 8 cntrl-2 edge/level control register irq0, and irq2 are connected to the interrupt controllers internally. the other interrupts are always generated externally. irq12 and irq13 may be generated internally through the abfull and ferr y signals, respec- tively. 152
82374eb/82374SB table 24. typical interrupt functions priority label controller typical interrupt source 1 irq0 1 interval timer 1, counter 0 out 2 irq1 1 keyboard 3-10 irq2 1 interrupt from controller 2 3 irq8 y 2 real time clock 4 irq9 2 expansion bus pin b04 5 irq10 2 expansion bus pin d03 6 irq11 2 expansion bus pin d04 7 irq12 2 expansion bus pin d05 8 irq13 2 coprocessor error, chaining 9 irq14 2 fixed disk drive controller expansion bus pin d07 10 irq15 2 expansion bus pin d06 11 irq3 1 serial port 2, expansion bus b25 12 irq4 1 serial port 1, expansion bus b24 13 irq5 1 parallel port 2, expansion bus b23 14 irq6 1 diskette controller, expansion bus b22 15 irq7 1 parallel port 1, expansion bus b21 9.1 interrupt controller internal registers several registers are contained internally within each 82c59. the interrupts at the irq input lines are handled by two registers in cascade, the interrupt request register (irr) and the in-service register (isr). the irr is used to store all the interrupt levels which are requesting service and the isr is used to store all the interrupt levels which are being serviced. internal circuitry determines the priorities of the bits set in the irr. the highest priority is selected and strobed into the corresponding bit of the isr during interrupt acknowledge cycles. the interrupt mask register (imr) stores the bits which mask the incoming interrupt lines. the imr operates on the irr. masking of a higher priority input will not effect the interrupt request lines of lower priority inputs. 9.2 interrupt sequence the powerful features of the interrupt controller in a microcomputer system are its programmability and the interrupt routine addressing capability. the latter allows direct or indirect jumping to the specific interrupt routine requested without any polling of the interrupting devices. the following shows the interrupt sequence for an x86 type system (the 8080 mode of the interrupt controller must never be selected when programming the esc). 153
82374eb/82374SB note that externally, the interrupt acknowledge cycle sequence appears different than in a traditional discrete 82c59 implementation. however, the traditional interrupt acknowledge sequence is generated within the esc and it is an eisa compatible implementation. 1. one or more of the interrupt request (irq [ x ] ) lines are raised high, setting the corresponding irr bit(s). 2. the interrupt controller evaluates these requests, and sends an intr to the cpu, if appropriate. 3. the cpu acknowledges the intr and responds with an interrupt acknowledge cycle. this cycle is translat- ed into a pci bus command. this pci command is broadcast over the pci bus as a single cycle as opposed to the two cycle method typically used. 4. upon receiving an interrupt acknowledge cycle from the cpu over the pci, the pceb converts the single cycle into an inta y pulse to the esc. the esc uses the inta y pulse to generate the two cycles that the internal 8259 pair can respond to with the expected interrupt vector. the cycle conversion is performed by a functional block in the esc interrupt controller unit. the internally generated interrupt acknowledge cycle is completed as soon as possible as the pci bus is held in wait states until the interrupt vector data is returned. each cycle appears as an interrupt acknowledge pulse on the inta y pin of the cascaded inter- rupt controllers. these two pulses are not observable at the esc periphery. 5. upon receiving the first internally generated interrupt acknowledge, the highest priority isr bit is set and the corresponding irr bit is reset. the interrupt controller does not drive the data bus during this cycle. on the trailing edge of the first cycle pulse, a slave identification code is broadcast by the master to the slave on a private, internal three bit wide bus. the slave controller uses these bits to determine if it must respond with an interrupt vector during the second inta y cycle. 6. upon receiving the second internally generated interrupt acknowledge, the interrupt controller releases an 8-bit pointer (the interrupt vector) onto the data bus where it is read by the cpu. 7. this completes the interrupt cycle. in the aeoi mode the isr bit is reset at the end of the second interrupt acknowledge cycle pulse. otherwise, the isr bit remains set until an appropriate eoi command is issued at the end of the interrupt subroutine. if no interrupt request is present at step four of either sequence (i.e., the request was too short in duration) the interrupt controller will issue an interrupt level 7. 9.3 80x86 mode when initializing the control registers of the 82c59, an option exists in initialization control word four (icw4) to select either an 80x86 or an msc-85 microprocessor based system. the interrupt acknowledge cycle is different in an msc-85 based system than in the 80x86 based system: the interrupt acknowledge takes three inta y pulses with the msc-85, rather than the two pulses with the 80x86. the esc is used only in an 80x86 based system. you must program each interrupt controller's icw4 bit 0 to a ``1'' to indicate that the interrupt controller is operating in an 80x86 based system. this setting ensures proper operation during an interrupt acknowledge. 9.3.1 esc interrupt acknowledge cycle as discussed, the cpu generates an interrupt acknowledge cycle that is translated into a single pci command and broadcast across the pci bus to the pceb. the pceb pulses the inta y signal to the esc. the esc interrupt unit translates the inta y signal into the two inta y pulses expected by the interrupt controller subsystem. the interrupt controller uses the first interrupt acknowledge cycle to internally freeze the state of the interrupts for priority resolution. the first controller (cntrl-1), as a master, issues a three bit interrupt code on the cascade lines to cntrl-2 (internal to the esc) at the end of the inta y pulse. on this first cycle the interrupt controller block does not issue any data to the processor and leaves its data bus buffers disabled. cntrl-2 decodes the information on the cascade lines, compares the code to the byte stored in initialization 154
82374eb/82374SB command word three (icw3), and determines if it will have to broadcast the interrupt vector during the second interrupt acknowledge cycle. on the second interrupt acknowledge cycle, the master (cntrl-1) or slave (cntrl-2), will send a byte of data to the processor with the acknowledged interrupt code composed as follows: table 25. content of interrupt vector byte for 80x86 system mode interrupt d7 d6 d5 d4 d3 d2 d1 d0 irq7,15 t7 t6 t5 t4 t3 1 1 1 irq6,14 t7 t6 t5 t4 t3 1 1 0 irq5,13 t7 t6 t5 t4 t3 1 0 1 irq4,12 t7 t6 t5 t4 t3 1 0 0 irq3,11 t7 t6 t5 t4 t3 0 1 1 irq2,10 t7 t6 t5 t4 t3 0 1 0 irq1,9 t7 t6 t5 t4 t3 0 0 1 irq0,8 t7 t6 t5 t4 t3 0 0 0 note: t7 t3 represent the interrupt vector address (refer register description section). the byte of data released by the interrupt unit onto the data bus is referred to as the ``interrupt vector''. the format for this data is illustrated on a per-interrupt basis in table 25. 9.4 programming the interrupt controller the interrupt controller accepts two types of command words generated by the cpu or bus master: 1. initialization command words (icws): before normal operation can begin, each interrupt controller in the system must be initialized. in the 82c59, this is a two to four byte sequence. however, for the esc, each controller must be initialized with a four byte sequence. this four byte sequence is required to configure the interrupt controller correctly for the esc implementation. this implementation is eisa-compatible. the four initialization command words are referred to by their acronyms: icw1, icw2, icw3, and icw4. the base address for each interrupt controller is a fixed location in the i/o memory space, at 0020h for cntrl-1 and at 00a0h for cntrl-2. an i/o write to the cntrl-1 or cntrl-2 base address with data bit 4 equal to 1 is interpreted as icw1. for esc-based eisa systems, three i/o writes to ``base address a 1'' (021h for cntrl-1 and 0a0h for cntrl-2) must follow the icw1. the first write to ``base address a 1'' (021h/0a0h) performs icw2, the second write performs icw3, and the third write performs icw4. 155
82374eb/82374SB icw1 starts the initialization sequence during which the following automatically occur: a. following initialization, an interrupt request (irq) input must make a low-to-high transition to generate an interrupt. b. the interrupt mask register is cleared. c. irq7 input is assigned priority 7. d. the slave mode address is set to 7. e. special mask mode is cleared and status read is set to irr. icw2 is programmed to provide bits [ 7:3 ] of the interrupt vector that will be released onto the data bus by the interrupt controller during an interrupt acknowledge. a different base [ 7:3 ] is selected for each interrupt controller. suggested values for a typical eisa system are listed in table 26. icw3 is programmed differently for cntrl-1 and cntrl-2, and has a different meaning for each control- ler. for cntrl-1, the master controller, icw3 is used to indicate which irqx input line is used to cascade cntrl-2, the slave controller. within the esc interrupt unit, irq2 on cntrl-1 is used to cascade the intr output of cntrl-2. consequently, bit 2 of icw3 on cntrl-1 is set to a 1, and the other bits are set to 0's. for cntrl-2, icw3 is the slave identification code used during an interrupt acknowledge cycle. cntrl-1 broadcasts a code to cntrl-2 over three internal cascade lines if an irq [ x ] line from cntrl-2 won the priority arbitration on the master controller and was granted an interrupt acknowledge by the cpu. cntrl-2 compares this identification code to the value stored in icw3, and if the code is equal to bits [ 2:0 ] of icw3, cntrl-2 assumes responsibility for broadcasting the interrupt vector during the second interrupt acknowl- edge cycle pulse. icw4 must be programmed on both controllers. at the very least, bit 0 must be set t oa1to indicate that the controllers are operating in an 80x86 system. 2. operation command words (ocws): these are the command words which dynamically reprogram the interrupt controller to operate in various interrupt modes. any interrupt lines can be masked by writing an ocw1. a 1 written in any bit of this command word will mask incoming interrupt requests on the corresponding irqx line. ocw2 is used to control the rotation of interrupt priorities when operating in the rotating priority mode and to control the end of interrupt (eoi) function of the controller. ocw3 is used to set up reads of the isr and irr, to enable or disable the special mask mode (smm), and to set up the interrupt controller in polled interrupt mode. the ocws can be written into the interrupt controller any time after initialization. table 26 shows an example of typical values programmed by the bios at power-up for the esc interrupt controller. 156
82374eb/82374SB table 26. suggested default values for interrupt controller registers port value description of contents 020h 11h cntlr-1, icw1 021h 08h cntlr-1, icw2 vector address for 000020h 021h 04h cntlr-1, icw3 indicates slave connection 021h 01h cntlr-1, icw4 8086 mode 021h b8h cntlr-1, interrupt mask (may vary) 4d0h 00h cntlr-1, edge/level control register 0a0h 11h cntlr-2, icw1 0a1h 70h cntlr-2, icw2 vector address for 0001c0h 0a1h 02h cntlr-2, icw3 indicates slave id 0a1h 01h cntlr-2, icw4 8086 mode 4d1h 00h cntlr-2, edge/level control register 0a1h bdh cntlr-2, interrupt mask (may vary) figure 20 illustrates the sequence software must follow to load the interrupt controller initialization command words (icws). the sequence must be executed for cntrl-1 and cntrl-2. after writing icw1, icw2, icw3, and icw4 must be written in order. any divergence from this sequence, such as an attempt to program an ocw, will result in improper initialization of the interrupt controller and unexpected, erratic system behavior. it is suggested that cntrl-2 be initialized first, followed by cntrl-1. in the esc, it is required that all four initialization command words (icws) be initialized. as shown in figure 20, all icws must be programmed prior to programming the ocws. 157
82374eb/82374SB 290476 82 figure 20. initialization sequence for esc initialization command words (icws) 9.5 end-of-interrupt operation 9.5.1 end of interrupt (eoi) the in service (is) bit can be reset either automatically following the trailing edge of the second internal inta y pulse (when aeoi bit in icw1 is set) or by a command word that must be issued to the interrupt controller before returning from a service routine (eoi command). an eoi command must be issued twice with this cascaded interrupt controller configuration, once for master and once for the slave. 158
82374eb/82374SB there are two forms of eoi commands: specific and non-specific. when the interrupt controller is operated in modes which preserve the fully nested structure, it can determine which is bit to reset on eoi. when a non- specific eoi command is issued, the interrupt controller will automatically reset the highest is bit of those that are set, since in the fully nested mode the highest is level was necessarily the last level acknowledged and serviced. a non-specific eoi can be issued with ocw2 (eoi e 1, sl e 0, r e 0). when a mode is used which may disturb the fully nested structure, the interrupt controller may no longer be able to determine the last level acknowledged. in this case a specific end of interrupt must be issued which includes as part of the command the is level to be reset. a specific eoi can be issued with ocw2 (eoi e 1, sl e 1, r e 0, and l0-l2 is the binary level of the is bit to be reset). it should be noted that an is bit that is masked by an imr bit will not be cleared by a non-specific eoi if the interrupt controller is in the special mask mode. 9.5.2 automatic end of interrupt (aeoi) mode if aeoi e 1 in icw4, then the interrupt controller will operate in aeoi mode continuously until reprogrammed by icw4. note that reprogramming icw4 implies that icw1, icw2, and icw3 must be reprogrammed first, in sequence. in this mode the interrupt controller will automatically perform a non-specific eoi operation at the trailing edge of the last interrupt acknowledge pulse. note that from a system standpoint, this mode should be used only when a nested multilevel interrupt structure is not required within a single interrupt controller. the aeoi mode can only be used in a master interrupt controller and not a slave (on cntrl-1 but not cntrl-2). 9.6 modes of operation 9.6.1 fully nested mode this mode is entered after initialization unless another mode is programmed. the interrupt requests are ordered in priority from 0 through 7 (0 being the highest). when an interrupt is acknowledged the highest priority request is determined and its vector placed on the bus. additionally, a bit of the interrupt service register (is [ 0:7 ] ) is set. this is bit remains set until the microprocessor issues an end of interrupt (eoi) command immediately before returning from the service routine. or, if the aeoi (automatic end of interrupt) bit is set, this is bit remains set until the trailing edge of the second internal inta y . while the is bit is set, all further interrupts of the same or lower priority are inhibited, while higher levels will generate an interrupt (which will be acknowledged only if the microprocessor internal interrupt enable flip-flop has been re-enabled through software). after the initialization sequence, irq0 has the highest priority and irq7 the lowest. priorities can be changed, as will be explained, in the rotating priority mode. 159
82374eb/82374SB 9.6.2 the special fully nested mode this mode will be used in the case of a big system where cascading is used, and the priority has to be conserved within each slave. in this case the special fully nested mode will be programmed to the master (using icw4). this mode is similar to the normal nested mode with the following exceptions: 1. when an interrupt request from a certain slave is in service, this slave is not locked out from the master's priority logic and further interrupt requests from higher priority irq's within the slave will be recognized by the master and will initiate interrupts to the processor. (in the normal nested mode a slave is masked out when its request is in service and no higher requests from the same slave can be serviced.) 2. when exiting the interrupt service routine the software has to check whether the interrupt serviced was the only one from that slave. this is done by sending a non-specific end of interrupt (eoi) command to the slave and then reading its in-service register and checking for zero. if it is empty, a non-specific eoi can be sent to the master too. if not, no eoi should be sent. 9.6.3 automatic rotation (equal priority devices) in some applications there are a number of interrupting devices of equal priority. automatic rotation mode provides for a sequential 8-way rotation. in this mode a device receives the lowest priority after being serviced. in the worst case, a device requesting an interrupt will have to wait until each of seven other devices are serviced at most once. figure 21 shows an example of automatic rotation. 290476 84 figure 21. automatic rotation mode example 160
82374eb/82374SB there are two ways to accomplish automatic rotation using ocw2, the rotation on non-specific eoi com- mand (r e 1, sl e 0, eoi e 1) and the rotate in automatic eoi mode which is set by (r e 1, sl e 0, eoi e 0) and cleared by (r e 0, sl e 0, eoi e 0). 9.6.4 specific rotation (specific priority) the programmer can change priorities by programming the bottom priority and thus fixing all other priorities. for example, if irq5 is programmed as the bottom priority device, then irq6 will be the highest priority device. the set priority command is issued in ocw2 where: r e 1, sl e 1; l0 l2 is the binary priority level code of the bottom priority device. see the register description for the bit definitions. note that in this mode internal status is updated by software control during ocw2. however, it is independent of the end of interrupt (eoi) command (also executed by ocw2). priority changes can be executed during an eoi command by using the rotate on specific eoi command in ocw2 (r e 1, sl e 1, eoi e 1 and l0 l2 e irq level to receive bottom priority). 9.6.5 poll command the polled mode can be used to conserve space in the interrupt vector table. multiple interrupts that can be serviced by one interrupt service routine do not need separate vectors if the service routine uses the poll command. the polled mode can also be used to expand the number of interrupts. the polling interrupt service routine can call the appropriate service routine, instead of providing the interrupt vectors in the vector table. in this mode the intr output is not used and the microprocessor internal interrupt enable flip-flop is reset, disabling its interrupt input. service to devices is achieved by software using a poll command. the poll command is issued by setting p e 1 in ocw3. the interrupt controller treats the next i/o read pulse to the interrupt controller as an interrupt acknowledge, sets the appropriate is bit if there is a request, and reads the priority level. interrupts are frozen from the i/o write to the i/o read. the word enabled onto the data bus during i/o read is shown in figure 22. 290476 85 notes: 1.w0 w2 : binary code of the highest priority level requesting service. 2.d [ 7:1 ] equal to 1 if there is an interrupt. figure 22. polled mode this mode is useful if there is a routine command common to several levels so that the inta y sequence is not needed (saves rom space). 9.6.6 cascade mode the interrupt controllers in the esc system are interconnected in a cascade configuration with one master and one slave. this configuration can handle up to 15 separate priority levels. the master controls the slaves through a three line internal cascade bus. when the master drives 010b on the cascade bus, this bus acts like a chip select to the slave controller. 161
82374eb/82374SB in a cascade configuration, the slave interrupt outputs are connected to the master interrupt request inputs. when a slave request line is activated and afterwards acknowledged, the master will enable the corresponding slave to release the interrupt vector address during the second inta y cycle of the interrupt acknowledge sequence. each interrupt controller in the cascaded system must follow a separate initialization sequence and can be programmed to work in a different mode. an eoi command must be issued twice: once for the master and once for the slave. 9.6.7 edge and level triggered modes there are two elcr registers, one for each 82c59 bank. they are located at i/o ports 04d0h (for the master bank, irq [ 0:1,3:7 ] ) and 04d1h (for the slave bank, irq [ 8 y :15 ] ). they allow the edge and level sense selection to be made on an interrupt by interrupt basis instead of on a complete bank. only the interrupts that connect to the eisa bus may be programmed for level sensitivity. that is irq (0,1,2,8 y ,13) must be pro- grammed for edge sensitive operation. the ltim bit is disabled in the esc. the default programming is equivalent to programming the ltim bit (icw1 bit 3) to a 0. if an elcr bit is equal to ``0'', an interrupt request will be recognized by a low to high transition on the corresponding irq input. the irq input can remain high without generating another interrupt. if an elcr bit is equal to ``1'', an interrupt request will be recognized by a ``low'' level on the corresponding irq input, and there is no need for an edge detection. for level triggered interrupt mode, the interrupt request signal must be removed before the eoi command is issued or the cpu interrupt must be disabled. this is necessary to prevent a second interrupt from occurring. in both the edge and level triggered modes the irq inputs must remain active until after the falling edge of the first inta y . if the irq input goes inactive before this time a default irq7 will occur when the cpu acknowledges the interrupt. this can be a useful safeguard for detecting interrupts caused by spurious noise glitches on the irq inputs. to implement this feature the irq7 routine is used for ``clean up'' simply executing a return instruction, thus ignoring the interrupt. if irq7 is needed for other purposes a default irq7 can still be detected by reading the isr. a normal irq7 interrupt will set the corresponding isr bit, a default irq7 won't. if a default irq7 routine occurs during a normal irq7 routine, however, the isr will remain set. in this case it is necessary to keep track of whether or not the irq7 routine was previously entered. if another irq7 occurs it is a default. irq13 still appears externally to be an edge sensitive interrupt even though it is shared internally with the chaining interrupt. the chaining interrupt is ored after the edge sense logic. 9.7 register functionality for a detailed description of the interrupt controller register set, please see section 3.4, interrupt controller register. 9.7.1 initialization command words four initialization command words (icws) are used to initialize each interrupt controller. each controller is initialized separately. following this initialization sequence, the interrupt controller is ready to accept interrupts. 162
82374eb/82374SB 9.7.2 operation control words (ocws) after the initialization command words (icws) are programmed into the interrupt controller, the chip is ready to accept interrupt requests at its input lines. however, interrupt controller operation can be dynamically modified to fit specific software/hardware expectations. different modes of operation are dynamically selected following initialization through the use of operation command words (ocws). 9.8 interrupt masks 9.8.1 masking on an individual interrupt request basis each interrupt request input can be masked individually by the interrupt mask register (imr). this register is programmed through ocw1. each bit in the imr masks one interrupt channel if it is set to a ``1''. bit 0 masks irq0, bit 1 masks irq1 and so forth. masking an irq channel does not effect the other channel's operation, with one notable exception. masking irq [ 2 ] on cntrl-1 will mask off all requests for service from cntrl-2. the cntrl-2 intr output is physically connected to the cntrl-1 irq [ 2 ] input. 9.8.2 special mask mode some applications may require an interrupt service routine to dynamically alter the system priority structure during its execution under software control. for example, the routine may wish to inhibit lower priority requests for a portion of its execution but enable some of them for another portion. the difficulty here is that if an interrupt request is acknowledged and an end of interrupt command did not reset its is bit (i.e., while executing a service routine), the interrupt controller would have inhibited all lower priority requests with no easy way for the routine to enable them. the special mask mode enables all interrupts not masked by a bit set in the mask register. interrupt service routines that require dynamic alteration of interrupt priorities can take advantage of the special mask mode. for example, a service routine can inhibit lower priority requests during a part of the interrupt service, then enable some of them during another part. in the special mask mode, when a mask bit is set in ocw1, it inhibits further interrupts at that level and enables interrupts from all other levels (lower as well as higher) that are not masked. thus, any interrupts may be selectively enabled by loading the mask register with the appropriate pattern. without special mask mode, if an interrupt service routine acknowledges an interrupt without issuing an eoi to clear the is bit, the interrupt controller inhibits all lower priority requests. the special mask mode provides an easy way for the interrupt service routine to selectively enable only the interrupts needed by loading the mask register. the special mask mode is set by ocw3 where: ssmm e 1, smm e 1, and cleared where ssmm e 1, smm e 0. 9.9 reading the interrupt controller status the input status of several internal registers can be read to update the user information on the system. the interrupt request register (irr) and in-service register (isr) can be read via ocw3, as discussed in section 3.7. the interrupt mask register (imr) is read via a read of ocw1, as discussed in section 3.7. here are brief descriptions of the isr, the irr, and the imr. 163
82374eb/82374SB interrupt request register (irr): 8-bit register which contains the status of each interrupt request line. bits that are clear indicate interrupts that have not requested service. the interrupt controller clears the irr's highest priority bit during an interrupt acknowledge cycle. (not effected by imr). in-service register (isr): 8-bit register indicating the priority levels currently receiving service. bits that are set indicate interrupts that have been acknowledged and their interrupt service routine started. bits that are cleared indicate interrupt requests that have not been acknowledged, or interrupt request lines that have not been asserted. only the highest priority interrupt service routine executes at any time. the lower priority interrupt services are suspended while higher priority interrupts are serviced. the isr is updated when an end of interrupt command is issued. interrupt mask register (imr): 8-bit register indicating which interrupt request lines are masked. the irr can be read when, prior to the i/o read cycle, a read register command is issued with ocw3 (rr e 1, ris e 0). the isr can be read when, prior to the i/o read cycle, a read register command is issued with ocw3 (rr e 1, ris e 1). the interrupt controller retains the isr/irr status read selection following each write to ocw3. therefore, there is no need to write an ocw3 before every status read operation, as long as the current status read corresponds to the previously selected register. for example, if the isr is selected for status read by an ocw3 write, the isr can be read over and over again without writing to ocw3 again. however, to read the irr, ocw3 will have to be reprogrammed for this status read prior to the ocw3 read to check the irr. this is not true when poll mode is used. polling mode overrides status read when p e 1, rr e 1 in ocw3. after initialization, the interrupt controller is set to read the irr. as stated, ocw1 is used for reading the imr. the output data bus will contain the imr status whenever i/o read is active. the address is 021h or 061h (ocw1). 9.10 non-maskable interrupt (nmi) an nmi is an interrupt requiring immediate attention and has priority over the normal interrupt lines (irqx). the esc indicates error conditions by generating a non-maskable interrupt. the esc generates nmi interrupts based on the following hardware and software events. hardware events: 1. motherboard parity errors: memory parity errors for the motherboard memory. these errors are reported to the esc through the perr y signal line. 2. system errors: system error on the motherboard. the system board uses the serr y signal to indicate system errors to the esc. 3. add-in board parity errors: parity errors on the add-in memory boards on the eisa expansion bus. iochk y signal on the eisa bus is driven low by the add-in board logic when this error occurs. 4. fail-safe timer timeout: fail-safe timer (timer 2, counter 0) count expires. if this counter has been set and enabled, and the count expires before a software routine can reset the counter. 5. bus timeout: an eisa bus master or slave exceeds the allocated time on the bus. a bus timeout occurs if an eisa master does not relinquish the bus (mreq y negated) within 64 bclks after it has been preempt- ed (mack y negated). a bus timeout also occurs if a memory slave extends the cycle (chrdy negated) long enough to keep cmd y asserted for more than 256 bclks. the dma controller does not cause a bus timeout. the esc asserts resdrv when a bus timeout occurs. 164
82374eb/82374SB software events: 1. software generated nmi: if an i/o write access to port 0462h occurs. the data value for this write is a don't care. the nmi logic incorporates four different 8-bit registers. these registers are used by the cpu to determine the source of the interrupt and to enable or disable/clear the interrupts. see section 3.4, interrupt controller registers, for the register details. table 27. nmi register i/o address map i/o port address register description 0061h nmi status register 0070h nmi enable register 0461h extended nmi register 0462h software nmi register table 28. nmi source enable/disable and status port bits nmi source io port bit for status reads io port bit for enable/disable perr y port 0061h, bit 7 port 0061h, bit 2 iochk y port 0061h, bit 6 port 0061h, bit 3 fail-safe port 0461h, bit 7 port 0461h, bit 2 bus timeout port 0461h, bit 6 port 0461h, bit 3 write to port 0462h port 0461h, bit 5 port 0461h, bit 1 the individual enable/disable bits clear the nmi detect flip-flops when disabled. all nmi sources can be enabled or disabled by setting port 070h bit [ 7 ] . this disable function does not clear the nmi detect flip-flops. this means, if nmi is disabled then enabled via port 070h, then an nmi will occur when port 070h is re-enabled if one of the nmi detect flip-flops had been previously set. to ensure that all nmi requests are serviced, the nmi service routine software needs to incorporate a few very specific requirements. these requirements are due to the edge detect circuitry of the host microprocessor, 80386 or 80486. the software flow would need to be the following: 1. nmi is detected by the processor on the rising edge of the nmi input. 2. the processor will read the status stored in port 061h and 0461h to determine what sources caused the nmi. the processor may then reset the register bits controlling the sources that it has determined to be active. between the time the processor reads the nmi sources and resets them, an nmi may have been generated by another source. the level of nmi will then remain active. this new nmi source will not be recognized by the processor because there was no edge on nmi. 3. the processor must then disable all nmi's by writing bit [ 7 ] of port 070h high and then enable all nmi's by writing bit [ 7 ] of port 070h low. this will cause the nmi output to transition low then high if there are any pending nmi sources. the cpu's nmi input logic will then register a new nmi. 165
82374eb/82374SB 10.0 advanced programmable interrupt controller (apic) in addition to the standard eisa compatible interrupt controller described in the previous section, the esc incorporates the advanced programmable interrupt controller (apic). while the standard interrupt controller is intended for use in a uni-processor system, apic can be used in either a uni-processor or multi-processor system. apic provides multi-processor interrupt management and incorporates both static and dynamic sym- metric interrupt distribution across all processors. in systems with multiple i/o subsystems, each subsystem can have its own set of interrupts. in a uni-processor system, apic's dedicated interrupt bus can reduce interrupt latency over the standard interrupt controller (i.e., the latency associated with the propagation of the interrupt acknowledge cycle across multiple busses using the standard interrupt controller approach). interrupts can be controlled by the standard eisa compatible interrupt controller unit, the i/o apic unit, or mixed mode where both the standard and i/o apic are used. the selection of which controller responds to an interrupt is determined by how the interrupt controllers are programmed. note that it is the programmer's responsibility to make sure that the same interrupt input signal is not handled by both interrupt controllers. at the system level, apic consists of two parts (figure 23)eone residing in the i/o subsystem (called the i/o apic) and the other in the cpu (called the local apic). the esc contains an i/o apic unit. the local apic and the i/o apic communicate over a dedicated apic bus. the esc's i/o apic bus interface consists of two bi-directional data signals (apicd [ 1:0 ] ) and a clock input (apicclk). the cpu's local apic unit contains the necessary intelligence to determine whether or not its processor should accept interrupts broadcast on the apic bus. the local unit also provides local pending of interrupts, nesting and masking of interrupts, and handles all interactions with its local processor (e.g., the intr/inta/ eoi protocol). the local unit further provides inter-processor interrupts and a timer, to its local processor. the register level interface of a processor to its local apic is identical for every processor. 290476 d6 figure 23. apic system structure 166
82374eb/82374SB the esc's i/o apic unit consists of a set of interrupt input signals, a 16-entry interrupt redirection table, programmable registers, and a message unit for sending and receiving apic messages over the apic bus (figure 24). i/o devices inject interrupts into the system by asserting one of the interrupt lines to the i/o apic (figure 25). the i/o apic selects the corresponding entry in the redirection table and uses the information in that entry to format an interrupt request message. each entry in the redirection table can be individually programmed to indicate edge/level sensitive interrupt signals, the interrupt vector and priority, the destination processor, and how the processor is selected (statically or dynamically). the information in the table is used to transmit a message to other apic units (via the apic bus). the esc's i/o apic contains a set of programmable registers. two of the registers (i/o register select and i/o window registers) are located in the cpu's memory space and are used to indirectly access the other apic registers as described in section 3.0, register description. the version register provides the implemen- tation version of the i/o apic. the i/o apic id register is programmed with an id value that serves as a physical name of the i/o apic. this id is loaded into the arb id register when the i/o apic id register is written and is used during bus arbitration. note: 1. when the esc's i/o apic receives an interrupt request, the esc instructs the pceb to flush its buffers and to request all system buffers pointing to pci to be flushed (via the aflush y signal). the apic does not send the interrupt message over the apic bus until the esc receives confirmation from the pceb (via the aflush y signal) that all buffers have been flushed and temporarily disabled. 2. the interrupt number or the vector does not imply a particular priority for being sent. the i/o apic continually polls the 16 interrupts in a rotating fashion, one at a time. the pending interrupt polled first is the one sent. 290476 d7 figure 24. apic register block diagram 167
82374eb/82374SB 290476 d8 figure 25. i/o apic interrupt mapping 10.1 physical characteristics of apic bus the apic bus is a 3-wire synchronous bus connecting all apics (all i/o units and all local units). two of these wires are used for data transmission, and one wire is a clock. for bus arbitration, the apic uses only one of the data wires. the bus is logically a wire-or and electrically an open-drain connection providing for both mes- sage transmission and arbitration for lowest priority. all the values mentioned in the protocol description are logical values (i.e. ``bus driven'' is logical 1 and ``bus not driven'' is logical 0). the electrical values are 0 for logical one and 1 for logical zero. 10.2 arbitration for apic bus the apic uses one wire arbitration to win the bus ownership. a rotating priority scheme is used for arbitration. the winner of the arbitration becomes the lowest priority agent and assumes an arbitration id of 0. all other agents, except the agent whose arbitration id is 15, increment their arbitration ids by one. the agent whose id was 15 takes the winner's arbitration id and increments it by one. arbitration ids are changed (incremented or assumed) only for messages that are transmitted successfully. for lowest priority messages, the arbitration id is updated before the final status cycle, which ultimately decides if the message is successful. a message is transmitted successfully if no cs error or acceptance error is reported for that message. an apic agent can acquire the bus using two different priority schemes; normal, or eoi (end of interrupt). eoi has the highest priority. eoi priority is used to send eoi messages for level interrupts from local apic to the i/o apic. when an agent requests the bus with eoi priority, all others requesting the bus with normal priorities back off. 168
82374eb/82374SB a bus arbitration cycle starts by the agent driving a start cycle (bit 1 e eoi, bit 0 e 1) on the apic bus (table 29). bit 1 e 1 indicates ``eoi'' priority and bit 1 e 0 indicates normal priority. bit 0 should be 1. in cycles 2 through 5, the agent drives the arbitration id on bit 1 of the bus. high-order id bits are driven first with successive cycles proceeding to the low bits of the id. all arbitration losers in a given cycle drop off the bus, using every subsequent cycle as a tie breaker for the previous cycle. when all arbitration cycles are completed, there will be only one agent left driving the bus. table 29. bus arbitration cycles cycle bit 1 bit 0 comments 1 eoi 1 0 1 e normal, 1 1 e eoi 2 arbid3 0 arbitration id bits 3 through 0 3 arbid2 0 4 arbid1 0 5 arbid0 0 10.3 bus message formats after bus arbitration the winner is granted exclusive use of the bus and drives its message on the bus. apic messages come in four formatse14 cycle eoi message, 21 cycles short message, 33 cycles lowest priority message, and 39 cycles remote read message. all apics on the apic bus know the length of an interrupt message by checking the appropriate fields in the message. eoi message for level triggered interrupts the eoi message is used to send an eoi cycle occurring for a level triggered interrupt from local apic to the i/o apic. this cycle contains the priority vector (v [ 7:0 ] ) of the interrupt. when this message is received, the i/o apic resets the remote irr bit for that interrupt. if the interrupt signal is still active after the rirr bit is reset, the i/o apic will treat it as a new interrupt. table 30. eoi message cycle bit 1 bit 0 comments 1 eoi 1 0 1 e normal, 1 1 e eoi 2 arbid3 0 arbitration id bits 3 through 0 3 arbid2 0 4 arbid1 0 5 arbid0 0 6 v7 v6 interrupt vector v7 v0 7v5 v4 8v3 v2 9v1 v0 169
82374eb/82374SB table 30. eoi message (continued) cycle bit 1 bit 0 comments 10 c c check sum 11 0 0 postamble 12 a a status cycle0 13 a1 a1 status cycle1 14 0 0 idle short message short messages are used for the delivery of fixed, nmi, smi (82374SB only), reset, extint and lowest priority with focus processor interrupts. the delivery mode bits (m [ 2:0 ] ) specify the message. all short mes- sages take 21 cycles, including the idle cycle. cycle 1 is the start cycle (table 31). cycles 2 through 5 are for bus arbitration as described earlier. apic id bits are sent on the bus one bit at a time (only one data bus bit is used). the other bit should be zero. cycles 6 and 7 provide destination mode and delivery mode bits. cycle 8 provides level and trigger mode information. cycles 10 through 13 are the 8-bit interrupt vector. the vector is only defined for delivery modes fixed, and lowest-priority. for delivery mode of ``remote read'', the vector field contains the address of the register to be read remotely. if destination mode (dm) is 0 (physical mode), then cycles 15 and 16 are the apic id and cycles 13 and 14 are zero. if dm is 1 (logical mode), then cycles 13 through 16 are the 8-bit destination field. the interpretation of the logical mode 8-bit destination field is performed by the local units using the destination format register. shorthands of ``all-incl-self'' and ``all-excl-self'' both use physical destination mode and a destination field containing apic id value of all ones. the sending apic knows whether it should (incl) or should not (excl) respond to its own message. cycle 17 is a checksum for the data in cycles 6 through 16. the (single) apic driving the message provides this checksum in cycle 17. cycle 18 is a postamble cycle driven as 00 by all apics to perform various internal computations based on the information contained in the received message. one of the computations takes the computed checksum of the data received in cycles 6 through 16 and compares it against the value in cycle 17. if any apic computes a different checksum than the one passed in cycle 17, then that apic signals an error on the apic bus in cycle 19 by driving it as 11. if this happens, all apics assume the message was never sent and the sender must try sending the message again, which includes re-arbitrating for the apic bus. in lowest priority delivery when the interrupt has a focus processor, the focus processor signals this by driving 10 during cycle 19. this tells all the other apics that the interrupt has been accepted, the lp arbitration is preempted, and short message format is used. cycle 19 and 20 indicates the status of the message (i.e. accepted, check sum error, retry or error). table 32 shows the status signals combinations and their meanings for all delivery modes. the checksum is calculated iteratively on each cycle by adding the following terms: 1. the two least significant bits from the last cycle's checksum. 2. the current two data bits. 3. the carry bit from the last cycle's checksum shifted to the least significant bit. note that, at the beginning of the calculation, the three bits composing the previous cycle's checksum (two lower bits and carry) are zero. 170
82374eb/82374SB table 31. short message cycle bit 1 bit 0 comments 10 1 01 e normal, 1 1 e eoi 2 arbid3 0 arbitration id bits 3 through 0 3 arbid2 0 4 arbid1 0 5 arbid0 0 6dm m2dm e destination mode 7 m1 m0 m2m0 e delivery mode 8 l tm l e level, tm e trigger mode 9 v7 v6 v7v0 e interrupt vector 10 v5 v4 11 v3 v2 12 v1 v0 13 d7 d6 destination 14 d5 d4 15 d3 d2 16 d1 d0 17 c c checksum for cycles 6 16 18 0 0 postamble 19 a a status cycle 0 20 a1 a1 status cycle 1 21 0 0 idle 171
82374eb/82374SB table 32. apic bus message status information delivery focus status: comments status: comments mode processor a a a1 a1 fixed, eoi n/a 00 cs is ok 10 accepted fixed, eoi n/a 00 cs is ok 11 retry fixed, eoi n/a 00 cs is ok 0x error fixed, eoi n/a 11 cs error xx fixed, eoi n/a 10 error xx fixed, eoi n/a 01 error xx nmi, smm, reset, extint n/a 00 cs is ok 10 accepted nmi, smm, reset, extint n/a 00 cs is ok 11 error nmi, smm, reset, extint n/a 00 cs is ok 0x error nmi, smm, reset, extint n/a 11 cs error xx nmi, smm, reset, extint n/a 10 cs error xx nmi, smm, reset, extint n/a 01 cs error xx lowest priority no 00 cs is ok. no focus processor 11 go for lp arb. lowest priority no 00 cs is ok. no focus processor 10 end and retry lowest priority no 00 cs is ok. no focus processor 0x error lowest priority yes 10 cs is ok. focus processor xx lowest priority yes 11 cs error xx lowest priority yes 01 error xx remote read n/a 00 cs is ok xx remote read n/a 11 cs error xx remote read n/a 01 error xx remote read n/a 10 error xx note: cs e check sum 172
82374eb/82374SB lowest priority (lp) without focus processor (fp) message this message format is used to deliver an interrupt in the lowest priority mode in which it does not have a focus processor. cycles 1 through 20 for this message are the same as for the short message discussed above. status cycle 19 identifies if there is not a focus processor (00) and a status value of 11 in cycle 20 indicates the need for lowest priority arbitration. cycle 21 through 28 are used to arbitrate for the lowest priority processor. the processors that take part in the arbitration drive their processor priority on the bus. only the local apics that have ``free interrupt slots'' participate in the lowest priority arbitration. cycle 29 through 32 are used to break a tie in case two or more processors have lowest priority. the bus arbitration ids are used to break the tie. cycle 33 is an additional status cycle driven by the accepting local apic. by receiving 10 during this cycle, the sending i/o apic knows that there was a local apic left after lp arbitration. otherwise, the message is retried. cycle 34 is an idle cycle. table 33. lowest priority without focus processor message cycle bit 1 bit 0 10 1 01 e normal, 1 1 e eoi 2 arbid3 0 arbitration id bits 3 through 0 3 arbid2 0 4 arbid1 0 5 arbid0 0 6dm m2dm e destination mode 7 m1 m0 m2m0 e delivery mode 8 l tm l e level, tm e trigger mode 9 v7 v6 v7v0 e interrupt vector 10 v5 v4 11 v3 v2 12 v1 v0 13 d7 d6 destination 14 d5 d4 15 d3 d2 16 d1 d0 17 c c checksum for cycles 6-16 18 0 0 postamble 19 a a status cycle 0 20 a1 a1 status cycle 1 173
82374eb/82374SB table 33. lowest priority without focus processor message (continued) cycle bit 1 bit 0 21 p7 0 inverted processor priority p7 p0 22 p6 0 23 p5 0 24 p4 0 25 p3 0 26 p2 0 27 p1 0 28 p0 0 29 arbid3 0 arbitration id 3 -0 30 arbid2 0 31 arbid1 0 32 arbid0 0 33 s s status (10 means status ok; all other values indicate an error) 34 0 0 idle remote read message the remote read message (table 34) is used for a local apic to read the register in another local apic. the message format is the same as the short message for the first 20 cycles. cycles 21 through 36 contain the remote register data. the status information in cycle 37 specifies if the data is good or not. the remote read message is always successful in that it is never retried (although the data may be valid or invalid). the reason is that the remote read message is a debug feature, and a ``hung'' remote apic that is unable to respond should not cause the debugger to hang up. table 34. remote read message cycle bit 1 bit 0 10 1 01 e normal, 1 1 e eoi 2 arbid3 0 arbitration id bits 3 through 0 3 arbid2 0 4 arbid1 0 5 arbid0 0 6dm m2dm e destination mode 7 m1 m0 m2m0 e delivery mode 8 l tm l e level, tm e trigger mode 174
82374eb/82374SB table 34. remote read message (continued) cycle bit 1 bit 0 9 v7 v6 v7v0 e interrupt vector 10 v5 v4 11 v3 v2 12 v1 v0 13 d7 d6 destination 14 d5 d4 15 d3 d2 16 d1 d0 17 c c checksum for cycles 6-16 18 0 0 postamble 19 a a status cycle 0 20 a1 a1 status cycle 1 21 d31 d30 remote register data 31-0 22 d29 d28 23 d27 d26 24 d25 d24 25 d23 d22 26 d21 d20 27 d19 d18 28 d17 d16 29 d15 d14 30 d13 d12 31 d11 d10 32 d09 d08 33 d07 d06 34 d05 d04 35 d03 d02 36 d01 d00 37 s s data status: 11 e valid, 00 e invalid 38 c c check sum for data d [ 31:00 ] 39 0 0 idle 175
82374eb/82374SB 11.0 pceb/esc interface the pceb/esc interface (figure 26) provides the inter-chip communications between the pceb and esc. the interface provides control information between the two components for pci/eisa arbitration, data size translations (controlling the pceb's eisa data swap logic), and interrupt acknowledge cycles. 290476 86 note: stpgnt y is only on the 82374SB (and companion 82375sb). figure 26. pceb/esc interface signals 11.1 arbitration control signals the pceb contains the arbitration circuitry for the pci bus and the esc contains the arbitration circuitry for the eisa bus. the pceb/esc interface contains a set of arbitration control signals (eisahold, eisaholda, nmflush y , and pereq y /inta y ) that synchronize bus arbitration and ownership changes between the two bus environments. the signals also force pci device data buffer flushing, if needed, to maintain data coherency during eisa bus ownership changes. the pceb is the default owner of the eisa bus. if another eisa/isa master or dma wants to use the bus, the esc asserts eisahold to instruct the pceb to relinquish eisa bus ownership. the pceb completes any current eisa bus transaction, tri-states its eisa bus signals, and asserts eisaholda to inform the esc that the pceb is off the bus. for ownership changes, other than for a refresh cycle, the esc asserts the nmflush y signal to the pceb (for one pciclk) to instruct the pceb to flush its line buffers pointing to the pci bus. the assertion of nmflush y also instructs the pceb to initiate flushing and to temporarily disable system buffers on the pci bus (via memreq y , memack, and flshreq y ). the buffer flushing maintains data coherency, in the event that the new eisa bus master wants to access the pci bus. buffer flushing also prevents dead-lock conditions between the pci bus and eisa bus. since the esc/pceb does not know ahead of time, whether the new master is going to access the pci bus or a device on the eisa bus, buffers pointing to the pci bus are always flushed when there is a change of eisa bus ownership, except for refresh cycles. for refresh cycles, the esc 176
82374eb/82374SB controls the cycle and, thus, knows that the cycle is not an access to the pci bus and does not initiate a flush request to the pceb. after a refresh cycle, the esc always surrenders control of the eisa bus back to the pceb. nmflush y is a bi-directional signal that is negated by the esc when buffer flushing is not being requested. the esc asserts nmflush y to request buffer flushing. when the pceb samples nmflush y asserted, it starts driving the signal in the asserted state and begins the buffer flushing process. (the esc tristates nmflush y after asserting if for the initial 1 pciclk period.) the pceb keeps nmflush y asserted until all buffers are flushed and then it negates the signal for 1 pciclk. when the esc samples nmflush y negated, it starts driving the signal in the negated state, completing the handshake. when the esc samples nmflush y negated, it grants ownership to the winner of the eisa bus arbitration (at the time nmflush y was negated). note that for a refresh cycle, nmflush y is not asserted by the esc. 290476 87 figure 27. nmflush y protocol when the eisa master completes its transfer and gets off the bus (i.e., removes its request to the esc), the esc negates eisahold and the pceb, in turn, negates eisaholda. at this point, the pceb resumes its default ownership of the eisa bus. if a pci master requests access to the eisa bus while the bus is owned by a master other than the pceb, the pceb retries the pci cycle and requests ownership of the eisa bus by asserting pereq y /inta y to the esc. pereq y /inta y is a dual function signal that is a pceb request for the eisa bus (pereq y function) when eisaholda is asserted. in response to the pceb request for eisa bus ownership, the esc removes the grant to the eisa master. when the eisa master completes its current transactions and relinquishes the bus (removes its bus request), the esc negates eisahold and the pceb, in turn, negates eisaholda. at this point, a grant can be given to the pci device for a transfer to the eisa bus. note that the inta y function of the pereq y /inta y signal is described in section 11.5, interrupt acknowledge control. 177
82374eb/82374SB 11.2 system buffer coherency controleapic during an interrupt sequence, the system buffers must be flushed before the esc's i/o apic can send an interrupt message to the local apic (cpu's apic). the esc and pceb maintain buffer coherency when the esc receives an interrupt request for its i/o apic using the aflush y signal. 11.3 power management in response to the esc's stpclk y assertion, the cpu sends out a stop grant bus cycle to indicate that it has entered the stop grant state. the pceb informs the esc of the stop grant cycle using the stpgnt y signal. 11.4 eisa data swap buffer control signals the cycles in the eisa environment may require data size translations before the data can be transferred to its intermediate or final destination. as an example, a 32-bit eisa master write cycle to a 16-bit eisa slave requires a disassembly of a 32-bit dword into 16 bit words. similarly, a 32-bit eisa master read cycle to a 16-bit slave requires an assembly of two 16-bit words into a 32-bit dword. the pceb contains eisa data swap buffers to support data size translations on the eisa bus. the operation of the data swap logic is described in the pceb data sheet. the esc controls the operation of the pceb's data swap logic with the following pceb/ esc interface signals. these signals are outputs from the esc and inputs to the pceb. # sdcpyen [ 13,03:01 ] y # sdcpyup # sdoe [ 2:0 ] y # sdle [ 3:0 ] y copy enable outputs (sdcpyen [ 13,3:1 ] y ) these signals enable the byte copy operations between data byte lanes 0, 1, 2 and 3 as shown in the table 35. isa master cycles do not perform assembly/disassembly operations. thus, these cycles use sdcpyen [ 13,03:01 ] y to perform the byte routing and byte copying between lanes. eisa master cycles however, can have assembly/disassembly operations. these cycles use sdcpyen [ 13,03:01 ] y in conjunc- tion with sdcpyup and sdle [ 3:0 ] y . 178
82374eb/82374SB table 35. byte copy operations signal copy between byte lanes sdcpyen01 y byte 0 (bits [ 7:0 ] ) and byte 1 (bits [ 15:8 ] ) sdcpyen02 y byte 0 (bits [ 7:0 ] ) and byte 2 (bits [ 23:16 ] ) sdcpyen03 y byte 0 (bits [ 7:0 ] ) and byte 3 (bits [ 31:24 ] ) sdcpyen13 y byte 1 (bits [ 15:8 ] ) and byte 3 (bits [ 31:24 ] ) system data copy up (sdcpyup) sdcpyup controls the direction of the byte copy operations. when sdcpyup is asserted (high), active lower bytes are copied onto the higher bytes. the direction is reversed when sdcpyup is negated (low). system data output enable (sdoe [ 2:0 ] y ) these signals enable the output of the data swap buffers onto the eisa bus (table 36). sdoe [ 2:0 ] are re- drive signals in case of mis-matched cycles between eisa to eisa, eisa to isa, isa to isa and the dma cycles between the devices on eisa. table 36. output enable operations signal byte lane sdoe0 y applies to byte 0 (bits [ 7:0 ] ) sdoe1 y applies to byte 1 (bits [ 15:8 ] ) sdoe2 y applies to byte 2 and byte 3 (bits [ 31:16 ] ) system data to internal (pceb) data latch enables (sdle [ 3:0 ] y ) these signals latch the data from the eisa bus into the data swap latches. the data is then either sent to the pci bus via the pceb or re-driven onto the eisa bus. sdle [ 3:0 ] y latch the data from the corresponding eisa bus byte lanes during pci reads from eisa, eisa writes to pci, dma cycles between an eisa device and the pceb. these signals also latch data during mismatched cycles between eisa to eisa, eisa to isa, isa to isa, the dma cycles between the devices on eisa, and any cycles that require copying of bytes, as opposed to copying and assembly/disassembly. 11.5 interrupt acknowledge control pereq y /inta y (pci to eisa request or interrupt acknowledge) is a dual function signal and the selected function depends on the status of eisahlda. when eisahlda is negated, this signal is an interrupt acknowl- edge (inta y ) and supports interrupt processing. if interrupt acknowledge is enabled via the pceb's pcicon register and eisaholda is negated, the pceb asserts pereq y /inta y when a pci interrupt acknowledge cycle is being serviced. this informs the esc that the forwarded eisa i/o read from location 04h is an interrupt acknowledge cycle. thus, the esc uses this signal to distinguish between a request for the interrupt vector and a read of the esc's dma register located at 04h. the esc responds to the read request by placing the interrupt vector on sd [ 7:0 ] . 179
82374eb/82374SB 12.0 integrated support logic the esc integrates support logic for assorted functions for a typical eisa system board. the following func- tions are directly supported by the esc. # eisa address buffer control # coprocessor interface # bios interface # keyboard controller interface # real time clock interface # floppy disk controller interface # configuration ram interface # x-bus and ide decode note: the esc directly supports x-bus floppy disk controller and ide. if the ide resides on another bus (e.g., isa or pci bus), additional hardware (to modify the x-bus signals) is required to support the x-bus floppy disk controller. 12.1 eisa address buffer control the eisa bus consists of unlatched addresses (la [ 31:2 ] ) and latched addresses (sa [ 19:2 ] ). eisa devices generate or monitor la addresses, and isa devices generate or monitor sa addresses. three discrete f543s are used to generate the sa address from la and la addresses from sa addresses (figure 28). the esc generates the control signals sale y , lasaoe y , and salaoe y for the f543s. these signals control the direction of the address flow. for eisa master, dma, and refresh cycles the, the la addresses are generated by the master device, and the sa addresses are driven by the f543s. for isa master devices, the sa addresses are generated by the master device, and the la addresses by driven by the f543s. 180
82374eb/82374SB 290476 88 figure 28. eisa address buffers table 37. eisa address buffer control function signal cycle type eisa master isa master dma refresh sale y pulses low pulses pulses lasaoe y low high low low salaoe y high low high high 12.2 coprocessor interface the numeric coprocessor interface is designed to support pc/at compatible numeric coprocessor exception handling. the eisa clock divider configuration register bit 5 needs to be set t oa1in order to enable the coprocessor error support in the esc. the coprocessor interface consists of ferr y signal and ignne y signal. the ferr y signal and ignne y signals are connected directly to the floating point error pin and ignore floating point error pin of the cpu respectively. whenever an error during computation is detected, the cpu asserts the ferr y signal to the esc. the esc internally generates an interrupt on the irq13 line of the integrated interrupt controller. the result is a asserted intr signal to the cpu. 181
82374eb/82374SB when the esc detects an i/o write to the internal port 00f0h, the esc deasserts the internal irq13 line to the integrated interrupt controller. at the same time the esc asserts the ignne y signal. the esc keeps the ignne y signal asserted until the ferr y signal is negated by the cpu. if the coprocessor error support is enabled in the eisa clock divider configuration register then the esc irq13 pins cannot be used, and this pin should be tied to ground. 290476 89 figure 29. coprocessor interface waveform 12.3 bios interface the esc supports a total of 512 kbytes of bios memory. the esc asserts the lbioscs y signal for eisa or isa memory cycles decoded to be in the bios space. the 512 kbytes of bios includes the conventional 128 kbytes of bios and 384 kbytes of enlarged bios. the 128 kbytes of conventional bios is divided into multiple regions. each region can be independently enabled or disabled by setting the appropriate bits in the bios chip select a register and bios chip select b register. the 128 kbytes of conventional bios is also aliased at different locations within the memory space. refer to section 4.1, bios memory space, for details. the esc generates the lbioscs y signal by internally latching the output of the bios address decode with bale signal. the esc asserts the lbioscs y for all read cycles in the enabled bios memory space. the esc will assert lbioscs y signal for write cycles in the enabled bios memory space only if the bios chip select b register bit 3 is set to 1 (bios write enable). 12.4 keyboard controller interface the esc provides a complete interface to a glueless interface to a 8x42 keyboard controller. the esc keyboard controller interface consists of keyboard controller chip select (kybdcs y ) signal, mouse interrupt (abfull) signal. the esc also supports the fast keyboard commands for cpu reset (altrst y ) and ad- dress a20 enable (alta20) by integrating port 92h. 182
82374eb/82374SB the esc asserts the kybdcs y signal for i/o cycles to addresses 60h (82374eb/sb), 62h (82374eb only), 64h (82374eb/sb), and 66h (82374eb only) if the peripheral chip select a register bit 1 is set to 1. the esc uses the abfull signal to internally generate an interrupt request to the integrated interrupt controller on the irq12 line if eisa clock divisor register bit 4 is set to 1 (mouse interrupt enable). a low to high transition on the abfull signal is internally latched by the esc. the high level on this latch remains until a write to i/o port 60h is detected or the esc is reset. the altrst y is used to reset the cpu under software control. the esc altrst y signal needs to be and'ed externally with the reset signal from the keyboard controller. a write to the system control register (092h) bit 0 to set the bit t o a 1 from a 0 causes the esc to pulse the altrst y signal. altrst y is asserted for approximately 4 bclks. the esc will not pulse the altrst y signal if bit 0 has previously been set to a 1. 12.5 real time clock the esc provides a glueless interface for the real time clock in the system. the esc provides a real time clock address latch enable signal (rtcale), a real time clock read strobe(rtcrd y ), and a real time clock write strobe (rtcwr y ). the esc pulses the rtcale signal asserted for one and a half bclks when an i/o write to address 70h is detected. the esc asserts rtcrd y signal and rtcwr y signal for i/o read and write accesses to address 71h respectively. the esc also supports the power on password protection through the real time clock. the power on password protection is enabled by setting the system control register 092h bit 3 to a 1. the esc does not assert rtcrd y signal or rtcwr y signal for i/o cycles to 71h if the access are addressed to real time clock addresses (write to 70h) 36h to 3fh if the power on password protection is enabled. 12.6 floppy disk control interface the esc supports interface to the 82077(sl) floppy disk controller chip. the esc provides a floppy disk controller chip select signal (fdccs y ). the esc also provides a buffered drive interface (dskchg y ) signal. in addition, the esc generates the control for the disk light. the esc supports both the primary address range (03f0h 03f7h) and secondary address range (0370h 0377h) of the floppy disk controller. the state of peripheral chip select a register bit 5 determines which address range is decoded by the esc as access to floppy disk controller. if bit 5 is set to 0, the esc will decode the primary floppy disk controller address range. if bit 5 is set to 1, the esc will decode the second- ary floppy disk controller address range. the esc supports the drive interface signal. during i/o accesses to address 03f7h (primary) or 0377h (secondary), the esc drives the inverted state of the dskchg y signal on to the sd7 data line. the esc uses the dskchg y signal to determine if the floppy disk controller is present on the x-bus. if the dskchg y signal is samples low during reset, the esc will disable floppy disk controller support. the esc also supports the disk light function by generating the dlight y signal. if system control 092h register bit 6 or bit 7 is set to a 1, the esc will assert the dlight y signal. 183
82374eb/82374SB 12.7 configuration ram interface the esc provides the control signals for 8 kbytes of external configuration ram. the configuration ram is used for storing eisa configuration system parameters. the configuration ram is i/o mapped between location 0800h 08ffh. due to the i/o address constraint (256 byte addresses for 8 kbyte of ram) , the configuration ram is organized in 32 pages of 256 bytes each. the i/o port 0c00h is used to store the configuration ram page address. the esc integrates this port as configuration ram page register. during a read or a write to the configuration ram address space 0800h 08ffh, the esc drives the configuration ram page address by placing the content of the configuration ram page address register bits [ 4:0 ] on the eisa address line la [ 31:27 ] y . the esc will also assert the cramrd y signal or the cramwr y signal for i/o read and write accesses to i/o address 0800h 08ffh. the esc will only generate the configuration ram page address and assert the cramrd y signal and cramwr y signal if the peripheral chip select b register bit 7 is set to 1. 12.8 general purpose peripherals, ide, parallel port, and serial port interface the esc provides three dual function pins (gpcs [ 2:0 ] y .ecs [ 2:0 ] ). the functionality of these pins is selected through the configuration mode select register bit 4. if mode select register bit 4 is set to 0 the general purpose chip select functionality is selected. if mode select register bit 4 is set to 1, the encoded chip select functionality is selected. in general purpose chip select mode, the esc generates three general purpose chip selects (gpcs [ 2:0 ] y ). the decode for each general purpose chip selects is programmed through a set of three configuration regis- ters; general purpose chip select x base low address register, general purpose chip select x base high address register, and general purpose chip select x mask register. each general purpose peripheral can be mapped anywhere in the 64 kbytes of i/o address. the general purpose peripheral address range is program- mable from 1 byte to 256 bytes with 2 n granularity. in encoded chip select mode (esc [ 2:0 ] ), in addition to decoding the general purpose chip select 0 address and general purpose chip select 1 address, the esc also decodes ide, parallel ports, and serial ports addresses. the encoded chip select mode requires an external decoder like a f138 to generate the device chip selects from the esc [ 2:0 ] signals. the esc generates encoded chip selects for two serial ports, comacs y (ecs [ 2:0 ] e 000) and combcs y (esc [ 2:0 ] e 001). the esc supports serial port com1 and serial port com2. accesses to serial port com1 or serial port com2 are individually programmed through peripheral chip select b register bits [ 0:3 ] to gener- ate a encoded chip select for comacs y or combcs y . 290476 90 figure 30. encoded chip select decoder logic 184
82374eb/82374SB table 38. encoded chip select decode esc2 esc1 esc0 peripheral cs 0 0 0 comacs y 0 0 1 combcs y 0 1 0 lptcs y 0 1 1 idecs0 y 1 0 0 idecs1 y 1 0 1 gpcs0 y 1 1 0 gpcs1 y 1 1 1 idle state note: refer to section 4.5 for the address decode of the peripheral chip selects. 12.9 x-bus control and general purpose decode the x-bus is a secondary data bus buffered from the eisa bus. the x-bus is used to interface with peripheral devices that do not require a high speed interface. typically a discrete buffer device like a f245 is used to buffer the eisa bus from the x-bus. the esc provides two control signals, xbust/r y and xbusoe y , for the discrete f245 buffer. note: the esc directly supports x-bus floppy disk controller and x-bus ide hard disk controller. if ide resides elsewhere (e.g., isa bus or pci bus), additional hardware is required to support the x-bus floppy. the additional hardware is used to modify the x-bus control signals. figure 31 shows the logic needed to support an x-bus floppy disk with ide on the isa or pci bus. 290476 d9 figure 31 185
82374eb/82374SB 290476 91 figure 32. x-bus data buffer the xbust/r y signal controls the direction of the data flow of the f245. when the xbust/r y signal is high, the data direction of the f245 buffer is from the xd [ 7:0 ] bus to the sd [ 7:0 ] bus. the esc drives the xbust/r y signal high during eisa master i/o read cycles, isa master i/o read cycles, dma write cycles (write to memory), and memory read cycles decoded to be in the x-bus bios address space. the esc also drives the xbust/r y signal high for dma reads (reads from memory/writes to i/o) from the x-bus bios address space. the x-bus bios address space is defined as the enabled regions and enabled aliases of the bios memory space. see section 4.1, bios memory space, for detailed description of the bios memory map and the configuration bits. the xbusoe y signal controls outputs of the f245. when the xbusoe y signal is asserted, the f245 drives its a buffers or b buffers depending on the state of the xbust/r y signal. the esc asserts the xbusoe y signal for i/o cycles decoded to be in the address range of the peripherals supported by the esc if these peripherals are enabled in the peripheral chip select a register and peripheral chip select b register. 186
82374eb/82374SB 13.0 power management (82374SB) the esc has extensive power management capability permitting a system to operate in a low power state without being powered down. in a typical desktop personal computer there are two statesepower on and power-off. leaving a system powered on when not in use wastes power. the esc provides a fast on/off feature that creates a third state called fast off (figure 33). when in the fast off state, the system consumes less power than the power-on state. the esc's power management architecture is based on three functionssystem management mode (smm), clock control, and advanced power management (apm). software (called smm code) controls the transitions between the power on state and the fast off state. the esc invokes this software by generating an smi to the cpu (asserting the smi y signal). a variety of programmable events are provided that can generate an smi. the smm code places the system in either the power on state or the fast off state. a fast on event is an event that instructs the computer (via an smi to the cpu) to enter the power-on state in anticipation of system activity by the user. fast on events are programmable and include moving the mouse, pressing a key on the keyboard, an external hardware event, an incoming call to a system fax/modem, a rtc alarm, or the operating system. 290476 e0 figure 33. fast on/off flow 187
82374eb/82374SB 13.1 smm mode smm mode is invoked by asserting the smi y signal to the cpu. the esc provides a variety of programmable events that can generate an smi. when the cpu receives an smi, it enters smm mode and executes smm code out of smram. the smm code places the system in either the power on state or the fast off state. in the power on state, the computer system operates normally. in this state one of the four programmable events listed below can trigger an smi. 1. a global idle timer called the fast off timer expires (an indication that the end user has not used the computer for a programmed period of time). 2. the extsmi y pin is asserted. 3. an rtc alarm interrupt is detected. 4. the operating system issues an apm call. 13.2 smi sources the smi y signal can be asserted by hardware interrupt events, the fast off timer, an external smi event (extsmi y ), and software events (via the apmc and apms registers). enable/disable bits (in the smien register) permit each event to be individually masked from generating an smi. in addition, the smi y signal can be globally enabled/disabled in the smicntl register. status of the individual events causing an smi is provided in the smireq register. for detailed information on the smi control/status registers, refer to section 3.0, register description. hardware interrupt events hardware events (irq [ 12,8 y ,4,3,1 ] and the fast off timer) are enabled/disabled from generating an smi in the smien register. when enabled, the occurrence of the corresponding hardware event generates an smi (asserts the smi y signal), regardless of the current power state of the system. fast off timer the fast off timer is used to indicate (through an smi) that the system has been idle for a programmed period of time. the timer counts down from a programmed start value and when the count reaches 00h, can generate an smi. the timer decrement rate is 1 count every minute and is re-loaded each time a system event occurs. this counter should not be programmed to 00h. system events are programmable events that can keep the system in the power on state when there is system activity (figure 34). these events are indicated by the assertion of irq [ 15:9,8 y ,7:3,1:0 ] , nmi, or smi signals. the system event prevents the system from entering the fast off state by re-loading the fast off timer. in addition to system events, break events cause the system to transition from a fast off state to the power on state. system events (and break events) are enabled/disabled in the see register. when enabled and the associated hardware event occurs (signal is asserted), the fast off timer is re-loaded with its initial count. 188
82374eb/82374SB 290476 e1 figure 34. system events and the fast off timer extsmi y the extsmi y input pin provides the system designer the capability to invoke smm with external hardware. for example, the extsmi y input could be connected to a ``green button'' permitting the user to enter the fast off state by depressing a button. the extsmi y generation of an smi is enabled/disabled in the smien register. software events software events (accessing the apmx registers) indicate that the os is passing power management informa- tion to the smi handler. there are two advanced power management (apm) registerseapm control (apmc) and apm status (apms) registers. these registers permit software to generate an smi; by writing to the apmc register. for example, the apmc can be used to pass an apm command between apm os and bios and the apms register could be used to pass data between the os and the smi handler. for detailed descriptions of these registers, see section 3.0, register description. the two apm registers are located in normal i/o space. the pceb subtractively decodes pci accesses to these registers and forwards the accesses to the eisa bus. the apm registers are not accessible by eisa masters. note that the remaining power management registers are located in pci configuration space. 13.3 smi y and init interaction the smi y input to the cpu is an edge sensitive signal. when an s-series processor is reset (init asserted), the processor resets the smi y edge detect logic. after init is negated, it takes two clocks before the edge detect circuit can catch an edge. the esc only asserts smi y when init is negated. if the esc asserts smi y and then the init signal is sampled asserted, the esc negates smi y . 13.3.1 clock control the cpu can be put in a low power state by asserting the stpclk y signal. stpclk y is an interrupt to the cpu. however, for this type of interrupt, the cpu does not generate an interrupt acknowledge cycle. once the stpclk y interrupt is executed, the cpu enters the stop grant state. in this state, the cpu's internal clocks are disabled and instruction execution is stopped. the stop grant state is exited when the stpclk y signal is negated. 189
82374eb/82374SB software can assert stpclk y , if enabled via the smicntl register, by a read of the apmc register. note that stpclk y can also be periodically asserted by using clock scaling as described below. the esc automatically negates stpclk y when a break event occurs (if enabled in the see register) and the cpu stop grant special cycle has been received. software can negate stpclk y by disabling stpclk y in the smicntl register or by a write to the apmc register. note: 1. init is always enabled as a break event. otherwise, init acts exactly as other break events: e if stpclk y is negated when init is asserted, the stpclk high timer is reloaded. e if init is asserted when stpclk y is asserted but before the stop grant bus cycle, stpclk y negation waits until after the stop grant bus cycle. this happens after the cpu is reset when it samples stpclk y still asserted. e if init is asserted when stpclk y is asserted and after the stop grant bus cycle, stpclk y is negated immediately. this guarantees that stpclk y will be negated after the cpu is reset. 2. while the stpclk y signal is asserted, the external interrupts (nmi, smi y and int) may be asserted to the cpu. if intr is asserted, it will remain asserted until the cpu inta cycle is detected. if smi y (or nmi) is asserted, it remains asserted until the smi (or nmi) handler clears the esc's csmigate (or sets the esc's nmimask bit). thus, smi y , nmi and intr can be applied to the cpu independent of the stpclk y signal state. note that when smi y , nmi, and irqx are enabled as break events, the occurrence of the break event negates stpclk y . clock scaling (emulating clock division) clock scaling permits the esc to periodically place the cpu in a low power state. this emulates clock division. when clock scaling is enabled, the cpu runs at full frequency for a pre-defined time period and then is stopped for a pre-defined time period. the run/stop time interval ratio emulates the clock division effect from a power/performance point of view. however, clock scaling is more effective than dividing the cpu frequency. for example, if the cpu is in the stop grant state and a break event occurs, the cpu clock returns to full frequency. in addition, there is no recovery time latency to start the clock. two programmable 8-bit clock scale timer control registers set the stpclk y high (negate) and low (assert) times the ctltmrh and ctltmrl registers. the timer is clocked by a 32 m s internal clock. this allows a programmable timer interval for both the stpclk y high and low times of 0-8 ms. when enabled via the smicntl register, the stpclk y timer operates as follows: # when stpclk y is negated, the timer is loaded with the value in the ctltmrh register and starts counting down. when the timer reaches 00h, stpclk y is asserted. since the timer is re-loaded with the contents of the ctltmrh register every time stpclk y is negated (for break events or clock throttling), the stpclk y minimum inactive time is guaranteed. # when stpclk y is asserted, the timer is loaded with the value in the ctltmrl register. the timer does not begin to count until the stop grant special cycle is received. when the timer reaches 00h, stpclk y is negated. note that a break event also negates stpclk y . note: if stpclk y is negated and a break event occurs, the stpclk y timer is loaded with the value in the ctltmrh register. 190
82374eb/82374SB 13.4 stop grant special cycle the host-bridge (e.g. pcmc) translates the cpu's stop grant cycle into a pci special cycle. the pceb recognizes the stop grant pci special cycle and asserts stpgnt y low to esc for one pciclk. the esc does not start the stpclk low timer until stpgnt y is asserted. during halt or autohalt state, the p54c does not respond to stpclk y assertion with a stop grant cycle. however, during this state an intr, smi y or nmi y assertion causes the cpu to exit the halted state, and eventually recognize the stpclk y assertion with a stop grant cycle. the system design must guarantee that intr, smi y and nmi y assertion is not blocked outside of the chipset while stpclk y is asserted. otherwise, a potential deadlock situation will exist. 13.5 dual-processor power management support figure 35 depicts the power management support for dual-processor (dp) or p54ct upgrade processor configuration. the input signals of smi y , stpclk y , and nmi of both oem and upgrade sockets are tied together. 290476 e2 figure 35. dual processor system configuration 13.5.1 smi y delivery mechanism for uni or ct upgrade processor system configuration, smi y can either be delivered through the esc smi y signal or i/o apic. for the p54c/cm dual-processor configuration, smi y should be delivered through i/o apic only. ideally, the os will put the cm processor in autohalt after the cm processor received a fast-off smi y . the cm processor will wake up if any non-masked system events occur. 191
82374eb/82374SB 13.5.2 stpclk y tied to both sockets to support a glueless upgrade socket, it is necessary to tie stpclk y to both sockets. for p54c/ct proces- sor configuration, the p54ct processor will disable p54c and the toggling of stpclk y has no effect to p54c. for a p54c/cm dp configuration, the toggling of stpclk y effects both processors (unless the processor is in autohalt state). both processors respond with a stpgnt special bus cycle after recognizing stpclk y low. both of the stpgnt special bus cycles are passed onto pci by the pcmc as pci stpgnt special cycles. the pci stpgnt pci cycle causes the pceb component to assert the stpgnt y signal, depending on how the sce bit in pceb is programmed. the esc recognizes the first stpgnt y assertion, and negates stpclk y upon the stop clock timer expiration or a stop break event. 13.5.3 smi y /intr (apic mode) when the apic is used for interrupt delivery, additional considerations exist regarding ordering. if local inter- rupts (lint0/1) are used in apic mode, then the system can not guarantee an ordering between the local interrupts and any related smi y events. in dp mode, interrupts can generally be directed to a specific processor, which may not be the same proces- sor that the smi y is directed. the irq blocking logic in the esc still operates with apic delivery mode. thus, if an irq is enabled to cause an smi y event, it will be blocked until the csmigate is cleared, regardless of where the irq or smi is to be directed by the apic. 14.0 electrical characteristics 14.1 maximum ratings case temperature under bias b 65 cto110 c storage temperature b 65 cto150 c supply voltages with respect to ground b 0.5v to v cc a 0.5v voltage on any pin b 0.5v to v cc a 0.5v power dissipation 0.70w fully loaded 0.55w with four slots warning: stressing the device beyond the ``absolute maximum ratings'' may cause permanent damage. these are stress ratings only. operating beyond the ``operating conditions'' is not recommended and ex- tended exposure beyond ``operating conditions'' may affect reliability. 14.2 nand tree a nand tree is provided primarily for vil/vih testing. the nand tree is also useful for automated test equipment (ate) at board-level testing. the nand tree allows the tester to test the solder connections for each individual signal pin. the test pin, along with irq5 and irq3, activates the nand tree. asserting test causes the output pulse train to appear on the eisahold pin. irq5 must be driven high in order to enable the nand tree. the assertion of irq3 causes the esc to disable its buffers. 192
82374eb/82374SB the sequence of the ate test is as follows: 1. drive test low, irq3 high, and irq5 high. 2. drive each pin that is a part of the nand tree high. please note that not every pin is included in the tree. see table below for details. 3. starting at pin 165 (dlight y ) and continuing with pins 167, 168, etc., individually drive each pin low. expect eisahold to toggle after each corresponding input pin is toggled. the final pin in the tree is pin 100 (eisahold). not every pin is toggled in sequential order. please refer to the table for tree ordering. when irq3 is driven low, the test mode is exited, and the esc's buffers will be enabled. 4. before enabling the esc's buffers (via irq3), turn off tester drivers. 5. reset the esc prior to proceeding with further testing. 193
82374eb/82374SB table 39. nand tree cell order (82374eb) pin y name 165 dlight y 1 167 fdccs y 168 rtcwr y 169 rtcrd y 102 aflush y 106 refresh y 107 apicclk 108 apicd1 109 apicd0 110 iochk y 111 rstdrv 112 irq9 113 dreq2 114 nows y 115 chrdy y 116 smwtc y 121 smrdc y 122 iowc y 123 iorc y 125 dreq3 127 dreq1 135 irq7 136 irq6 141 bale 142 osc 143 sa1 144 sa0 145 m16 y 146 sbhe y 147 io16 y 148 irq10 pin y name 149 irq11 150 irq12 151 irq15 152 irq14 164 cramrd y 166 dskchg 171 abfull 179 cmd y 180 start y 186 exrdy 187 ex32 y 188 ex16 y 189 slburst y 190 eop 191 spkr 193 irq8 y 194 irq13 195 irq1 197 dreq0 198 mrdc y 200 mwtc y 201 dreq5 203 dreq6 205 dreq7 206 master16 y 3 la31 y /cpg4 4 la30 y /cpg3 5 la29 y /cpg2 6 la28 y /cpg1 7 la27 y /cpg0 8 la26 y 10 la25 y 194
82374eb/82374SB table 39. nand tree cell order (82374eb) (continued) pin y name 11 la24 y 12 la16 13 la15 15 la14 16 la13 17 la12 19 la11 20 la10 21 la9 22 la8 23 la7 24 la6 28 la5 29 la4 30 la23 31 la3 32 la22 33 la2 34 la21 36 la20 40 la19 42 mreq7 y /pirq0 y 43 la18 44 mreq6 y /pirq1 y 45 la17 46 mreq5 y /pirq2 y 47 mreq4 y /pirq3 y 48 mreq3 y pin y name 49 mreq2 y 50 mreq1 y 51 mreq0 y 55 be0 y 56 be1 y 57 be2 y 58 be3 y 59 sd0 60 sd1 61 sd2 63 sd3 64 sd4 65 sd5 66 sd6 67 sd7 70 w/r y 71 m/io y 72 msburst y 91 ferr y 95 reset y 96 perr y 97 serr y 98 nmflush y 99 pereq y /inta y 138 irq4 139 irq3 (2) 100 eisahold (3) 195
82374eb/82374SB table 40. nand tree cell order (82374SB) pin y name 165 dlight y (1) 167 fdccs y 168 rtcwr y 169 rtcrd y 170 rtcale 171 abfull 172 kybdcs y 173 lbioscs y 174 salaoe y 175 lasaoe y 176 sale y 102 aflush y 106 refresh y 107 apicclk 108 apicd1 109 apicd0 110 iochk y 111 rstdrv 112 irq9 113 dreq2 114 nows y 115 chrdy y 116 smwtc y 117 aen4 118 aen3 119 aen2 120 aen1 121 smrdc y 122 iowc y 123 iorc y 124 dack3 y pin y name 125 dreq3 126 dack1 y 127 dreq1 133 stpgnt y 134 aen y 135 irq7 136 irq6 140 dack2 y 141 bale 142 osc 143 sa1 144 sa0 145 m16 y 146 sbhe y 147 io16 y 148 irq10 149 irq11 150 irq12 151 irq15 152 irq14 155 gpcs0 y 159 gpcs1 y 160 gpcs2 y 161 xbusoe y 162 xbust/r y 163 cramwr y 164 cramrd y 166 dskchg 179 cmd y 180 start y 185 extsmi y 186 exrdy 196
82374eb/82374SB table 40. nand tree cell order (82374SB) (continued) pin y name 187 ex32 y 188 ex16 y 189 slburst y 190 eop 191 spkr 192 slowh y 193 irq8 y 194 irq13 195 irq1 196 dack0 y 197 dreq0 198 mrdc y 199 dack5 y 200 mwtc y 201 dreq5 202 dack6 y 203 dreq6 204 dack7 y 205 dreq7 206 master16 y 207 mack3 y 3 la31 y /cpg4 4 la30 y /cpg3 5 la29 y /cpg2 6 la28 y /cpg1 7 la27 y /cpg0 8 la26 y 10 la25 y 11 la24 y 12 la16 13 la15 15 la14 pin y name 16 la13 17 la12 19 la11 20 la10 21 la9 22 la8 23 la7 24 la6 28 la5 29 la4 30 la23 31 la3 32 la22 33 la2 34 la21 36 la20 37 mack2 y 38 mack1 y 40 la19 41 mack0 y 42 mreq7 y /pirq0 y 43 la18 44 mreq6 y /pirq1 y 45 la17 46 mreq5 y /pirq2 y 47 mreq4 y /pirq3 y 48 mreq3 y 49 mreq2 y 50 mreq1 y 51 mreq0 y 55 be0 y 56 be1 y 197
82374eb/82374SB table 40. nand tree cell order (82374SB) (continued) pin y name 57 be2 y 58 be3 y 59 sd0 60 sd1 61 sd2 63 sd3 64 sd4 65 sd5 66 sd6 67 sd7 70 w/r y 71 m/io y 72 msburst y 73 sdoe2 y 74 sdoe1 y 75 sdoe0 y 76 sdcpyup 80 sdcpyen13 y 81 sdcpyen03 y pin y name 82 sdcpyen02 y 83 sdcpyen01 y 84 sdle0 y 85 sdle1 y 86 sdle2 y 87 sdle3 y 91 ferr y 95 reset y 96 perr y 97 serr y 98 nmflush y 99 pereq y /inta y 138 irq4 139 irq3 (2) 100 eisahold (3) notes: 1. first pin in nand tree. 2. enables esc's buffers when 0. 3. last pin in nand tree. 198
82374eb/82374SB 15.0 pinout and package information the esc package is a 208-pin plastic quad flat pack (pqfp). the package signals are shown in figure 36 and listed in table 41 and table 42. note that nc pins require individual pull-up resistors of 8 k x 10 k x . 15.1 pinout and pin assignment 290476 d2 note: init, smi y , stpclk y , stpgnt y , extsmi y , are on the 82374SB only. figure 36. esc package pinout 199
82374eb/82374SB table 41. esc alphabetical pin assignment name pin y type abfull 171 in aen y 134 out aen1/eaen1 120 out aen2/eaen2 119 out aen3/eaen3 118 out aen4/eaen4 117 out aflush y 102 t/s alta20 94 out altrst y 93 out apicclk 107 in apicd0 y 109 od apicd1 y 108 od bale 141 out bclk 128 in bclkout 178 out be0 y 55 t/s be1 y 56 t/s be2 y 57 t/s be3 y 58 t/s chrdy 115 o/d cmd y 179 out cramrd y 164 out cramwr y 163 out dack0 y 196 out dack1 y 126 out dack2 y 140 out dack3 y 124 out dack5 y 199 out dack6 y 202 out dack7 y 204 out dlight y 165 out name pin y type dreq0 197 in dreq1 127 in dreq2 113 in dreq3 125 in dreq5 201 in dreq6 203 in dreq7 205 in dskchg 166 in eisahlda 100 in eisahold 101 out eop 190 t/s ex16 y 188 o/d ex32 y 187 o/d exrdy 186 o/d extsmi y (82374SB) 185 in fdccs y 167 out ferr y 91 in gpcs0 y /ecs0 155 out gpcs1 y /ecs1 159 out gpcs2 y /ecs2 160 out ignne y 92 out init/test (82374SB) 154 in intr 89 out io16 y 147 o/d iochk y 110 in iorc y 123 t/s iowc y 122 t/s irq1 195 in irq3 139 in irq4 138 in irq5 137 in 200
82374eb/82374SB table 41. esc alphabetical pin assignment (continued) name pin y type irq6 136 in irq7 135 in irq8 y 193 in irq9 112 in irq10 148 in irq11 149 in irq12 150 in irq13 194 in irq14 152 in irq15 151 in kybdcs y 172 out la2 33 t/s la3 31 t/s la4 29 t/s la5 28 t/s la6 24 t/s la7 23 t/s la8 22 t/s la9 21 t/s la10 20 t/s la11 19 t/s la12 17 t/s la13 16 t/s la14 15 t/s la15 13 t/s la16 12 t/s la17 45 t/s la18 43 t/s la19 40 t/s la20 36 t/s la21 34 t/s la22 32 t/s name pin y type la23 30 t/s la24 y 11 t/s la25 y 10 t/s la26 y 8 t/s la27 y /cpg0 7 t/s la28 y /cpg1 6 t/s la29 y /cpg2 5 t/s la30 y /cpg3 4 t/s la31 y /cpg4 3 t/s lasaoe y 175 out lbioscs y 173 out m/io y 71 t/s m16 y 145 o/d mack0 y / 41 out emack0 mack1 y / 38 out emack1 mack2 y / 37 out emack2 mack3 y / 207 out emack3 master16 y 206 in mrdc y 198 t/s mreq0 y 51 in mreq1 y 50 in mreq2 y 49 in mreq3 y 48 in mreq4 y pirq3 y 47 in mreq5 y /pirq2 y 46 in mreq6 y /pirq1 y 44 in mreq7 y /pirq0 y 42 in msburst y 72 t/s 201
82374eb/82374SB table 41. esc alphabetical pin assignment (continued) name pin y type mwtc y 200 t/s nc (82374eb) 132 e nc (82374eb) 133 e nc (82374eb) 184 e nc (82374eb) 185 e nmflush y 98 t/s nmi 90 out nows y 114 o/d osc 142 in pciclk 153 in pereq y /inta y 99 in perr y 96 in refresh y 106 t/s reset y 95 in rstdrv 111 out rtcale 170 out rtcrd y 169 out rtcwr y 168 out sa0 144 t/s sa1 143 t/s salaoe y 174 out sale y 176 out sbhe y 146 t/s sd0 59 t/s sd1 60 t/s sd2 61 t/s sd3 63 t/s sd4 64 t/s sd5 65 t/s sd6 66 t/s sd7 67 t/s sdcpyen01 y 83 out name pin y type sdcpyen02 y 82 out sdcpyen03 y 81 out sdcpyen13 y 80 out sdcpyup 76 out sdle0 y 84 out sdle1 y 85 out sdle2 y 86 out sdle3 y 87 out sdoe0 y 75 out sdoe1 y 74 out sdoe2 y 73 out serr y 97 in slburst y 189 in slowh y 192 out smi y (82374SB) 184 out smrdc y 121 out smwtc y 116 out spkr 191 out start y 180 t/s stpclk y (82374SB) 132 out stpgnt y (82374SB) 133 in test (82374eb) 154 in v dd 1v v dd 14 v v dd 25 v v dd 39 v v dd 52 v v dd 53 v v dd 68 v v dd 79 v v dd 104 v 202
82374eb/82374SB table 41. esc alphabetical pin assignment (continued) name pin y type v dd 105 v v dd 131 v v dd 156 v v dd 157 v v dd 181 v v dd 208 v v ss 2v v ss 9v v ss 18 v v ss 26 v v ss 27 v v ss 35 v v ss 54 v v ss 62 v name pin y type v ss 69 v v ss 77 v v ss 78 v v ss 88 v v ss 103 v v ss 129 v v ss 130 v v ss 158 v v ss 177 v v ss 182 v v ss 183 v w/r y 70 t/s xbusoe y 161 out xbust/r y 162 out 203
82374eb/82374SB table 42. esc numerical pin assignment name pin y type 1v dd v 2v ss v 3 la31 y /cpg4 t/s 4 la30 y /cpg3 t/s 5 la29 y /cpg2 t/s 6 la28 y /cpg1 t/s 7 la27 y /cpg0 t/s 8 la26 y t/s 9v ss v 10 la25 y t/s 11 la24 y t/s 12 la16 t/s 13 la15 t/s 14 v dd v 15 la14 t/s 16 la13 t/s 17 la12 t/s 18 v ss v 19 la11 t/s 20 la10 t/s 21 la9 t/s 22 la8 t/s 23 la7 t/s 24 la6 t/s 25 v dd v 26 v ss v 27 v ss v 28 la5 t/s name pin y type 29 la4 t/s 30 la23 t/s 31 la3 t/s 32 la22 t/s 33 la2 t/s 34 la21 t/s 35 v ss v 36 la20 t/s 37 mack2 y /emack2 out 38 mack1 y /emack1 out 39 v dd v 40 la19 t/s 41 mack0 y /emack0 out 42 mreq7 y /pirq0 y in 43 la18 t/s 44 mreq6 y /pirq1 y in 45 la17 t/s 46 mreq5 y /pirq2 y in 47 mreq4 y /pirq3 y in 48 mreq3 y in 49 mreq2 y in 50 mreq1 y in 51 mreq0 y in 52 v dd v 53 v dd v 54 v ss v 55 be0 y t/s 204
82374eb/82374SB table 42. esc numerical pin assignment (continued) name pin y type 56 be1 y t/s 57 be2 y t/s 58 be3 y t/s 59 sd0 t/s 60 sd1 t/s 61 sd2 t/s 62 v ss v 63 sd3 t/s 64 sd2 t/s 65 sd5 t/s 66 sd6 t/s 67 sd7 t/s 68 v dd v 69 v ss v 70 w/r y t/s 71 m/io y t/s 72 msburst y t/s 73 sdoe2 y out 74 sdoe1 y out 75 sdoe0 y out 76 sdcpyup out 77 v ss v 78 v ss v 79 v dd v 80 sdcpyen13 y out 81 sdcpyen03 y out 82 sdcpyen02 y out 83 sdcpyen01 y out 84 sdle0 y out 85 sdle1 y out 86 sdle2 y out 87 sdle3 y out name pin y type 88 v ss v 89 intr out 90 nmi out 91 ferr y in 92 ignne y out 93 altrst y out 94 alta20 out 95 reset y in 96 perr y in 97 serr y in 98 nmflush y t/s 99 pereq y / inta y in 100 eisahlda in 101 eisahold out 102 aflush y t/s 103 v ss v 104 v dd v 105 v dd v 106 refresh y t/s 107 apicclk in 108 apicd1 y od 109 apicd0 y od 110 iochk y in 111 rstdrv out 112 irq9 in 113 dreq2 in 114 nows y o/d 115 chrdy o/d 116 smwtc y out 117 aen4/eaen4 out 118 aen3/eaen3 out 119 aen2/eaen2 out 205
82374eb/82374SB table 42. esc numerical pin assignment (continued) name pin y type 120 aen1/eaen1 out 121 smrdc y out 122 iowc y t/s 123 iorc y t/s 124 dack3 y out 125 dreq3 in 126 dack1 y out 127 dreq1 in 128 bclk in 129 v ss v 130 v ss v 131 v dd v 132 nc (82374eb) e stpclk y (82374SB) out 133 nc (82374eb) e stpgnt y (82374SB) in 134 aen y out 135 irq7 in 136 irq6 in 137 irq5 in 138 irq4 in 139 irq3 in 140 dack2 y out 141 bale out 142 osc in 143 sa1 t/s 144 sa0 t/s 145 m16 y o/d 146 sbhe y t/s 147 io16 y o/d 148 irq10 in name pin y type 149 irq11 in 150 irq12 in 151 irq15 in 152 irq14 in 153 pciclk in 154 test (82374eb) in init/test (82374SB) in 155 gpcs0 y /ecs0 out 156 v dd v 157 v dd v 158 v ss v 159 gpcs1 y /ecs1 out 160 gpcs2 y /ecs2 out 161 xbusoe y out 162 xbust/r y out 163 cramwr y out 164 cramrd y out 165 dlight y out 166 dskchg in 167 fdccs y out 168 rtcwr y out 169 rtcrd y out 170 rtcale out 171 abfull in 172 kybdcs y out 173 lbioscs y out 174 salaoe y out 175 lasaoe y out 176 sale y out 177 v ss v 178 bclkout out 179 cmd y out 206
82374eb/82374SB table 42. esc numerical pin assignment (continued) name pin y type 180 start y t/s 181 v dd v 182 v ss v 183 v ss v 184 nc (82374eb) e smi y (82374SB) out 185 nc (82374eb) e extsmi y (82374SB) in 186 exrdy o/d 187 ex32 y o/d 188 ex16 y o/d 189 slburst y in 190 eop t/s 191 spkr out 192 slowh y out name pin y type 193 irq8 y in 194 irq13 in 195 irq1 in 196 dack0 y out 197 dreq0 in 198 mrdc y t/s 199 dack5 y out 200 mwtc y t/s 201 dreq5 in 202 dack6 y out 203 dreq6 in 204 dack7 y out 205 dreq7 in 206 master16 y in 207 mack3 y /emack3 out 208 v dd v 207
82374eb/82374SB 15.2 package characteristics 290476 d3 figure 37. packaging dimension information 208

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